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Introduction of the Driver Margining feature of the EMIF ToolKit

Introduction of the Driver Margining feature of the EMIF ToolKit

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Introduction

The EMIF Tool Kit has a function called Driver Margining. This article introduces this function and how to use it.

 

What is the Driver Margining function?

Driver Margining of the EMIF Tool Kit is 
a function to observe the read/write margin in user mode 
. 
Calibration also observes the read/write margin, but Driver Margining is 
a function to observe the read/write margin in user mode. /Write margining in user mode. 

The following document provides an overview: 
External Memory Interfaces Arria® 10 FPGA IP User Guide

  • https://docs.altera.com/r/5ybDUDNrbPzSEVSGXW2L4g/wvwCHUIVk~jQ3njUAV6CyQ

    = > 14.7.1.8. Driver Margining for Arria 10 EMIF IP 

    Using the Example Design as an example, the key points to use are as shown in the above document: 
    - Enable In-System Sources/Probes 
    Add the following setting to qsf: 
    set_global_assignment -name VERILOG_ MACRO "ALTERA_EMIF_ENABLE_ISSP=1" 
    ・Reset_n/Pass/Fail/PNF with In-System Sources/Probes 

     

Specific steps to perform Driver Margining functions

The specific steps are as follows

  1. Create an Example Design at the time of IP generation.
  2. Enable In-System Sources/Probes (add the above settings to qsf)
  3. Compile => Write to FPGA
  4. Open EMIF Toolkit and execute in the following order (1) to (5) 5.

　　Press "Driver Margining" in (5) above to display the following screen, and select the following signals in each item.

　Select the following signals in each item (the appearance may differ slightly depending on the version or edition of Quartus® Prime development software). 6.

　　After Driver Margining is finished, the Margin Report will be displayed in the report window. 
You can check the waveforms and other data from each report to see if there is any margin.

 

Reference

These procedures are also described in the following chapters of the User's Guide.

External Memory Interfaces Arria® 10 FPGA IP User Guide

 

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