Description.
As the speed of external memory interfaces (External Memory Interface/EMIF) increases, the shrinking of the data valid window and deterioration of signal quality have been cited as challenges.
Since the time spent on verification and debugging to meet the required specifications is on the rise, it is important to design device boards according to appropriate procedures and to implement means for debugging in advance during the design phase.
This document shows the design flow and debug flow, and was prepared with the aim of preventing the introduction of defects by following the proper design procedure and quickly solving problems by implementing the necessary mechanisms for debugging.
- Target device: Arria® 10 FPGA
- Target memory topologies: DDR4, DDR3
Contents
- Introduction
- Design Flow
- Debug Flow
- Appendix
- Checklist
- How to check DDR4 parameters
- How to Create an Example Design
- How to use EMIF ToolKit
Design and Debug Guidelines (Rev. 3.2) / Arria® 10 Edition