First of all
In FPGAs, Fmax changes with each compilation.
Especially when there are multiple clock systems, Clock_A did not meet the Fmax timing in the previous compilation, but in the next compilation, Clock_B and Clock_C do not meet the timing.
Furthermore, in the next compilation, Clock_B and Clock_D cannot satisfy the timing.
Only Clock_B needs to satisfy the timing.
Is there any way to get the timing convergence of the clocks that I want to prioritize when there are multiple clocks?
Is there a setting?
Yes, there is.
It is possible to perform priority placement by writing the following constraints in the qsf file of the Quartus® Prime development software and compiling the file.
set_instance_assignment -name SYNTH_CRITICAL_CLOCK ON -to <clock name>Although this setting does not always result in timing convergence, please try
as it will give priority to the specified clock for timing convergence.