1. introduction
This document describes an example of running the bare-metal sample application ALT-HWLib-HelloWorld-Unhosted-A10-GNU standalone from a QSPI (Quad SPI) boot Flash daughter card, which can be installed in the Arria® 10 SoC Development Kit.
This bare-metal sample application is a simple application that displays a "Hello from Arria 10 SoC!!!" message via UART. The file io.c included in this sample is also useful for stand-alone applications that redirect the output of printf() to the UART instead of JTAG.
This document describes the following.
(1) Important hardware development products (handoff files)
(2) SoC FPGA boot flow
(3) How to build bare-metal sample applications with Arm® Development Studio 5 Intel® SoC FPGA Edition (DS-5)
・ Starting DS-5
・ Importing bare metal sample application
・ Building bare metal sample application
(4) How to generate 2nd stage boot loader (U-Boot) for QSPI flash boot
・ What is 2nd stage boot loader?
・ How to generate 2nd stage boot loader for QSPI flash boot
(5) Example of standalone execution of bare-metal application from QSPI flash
・ How to write RBF file to QSPI flash
・ How to write 2nd stage boot loader and application image to QSPI Flash
・ Check operation of stand-alone execution
Point:
This document describes an example using mainly U-Boot as the 2nd stage boot loader.
You can also use the UEFI (Unified Extensible Firmware Interface) boot loader as a non-GPL-licensed boot loader source.
For more information about UEFI boot loaders, please refer to the Arria® 10 SoC UEFI BootLoader User Guide.
Point:
The hardware design described in this document uses an existing QSPI boot design for the Arria® 10 SoC FPGA Development Kit.
The main development environments used in this document are listed below.
[Table 1-1] Main development environments used in the descriptions in this document
| Item No. | Item | Description |
| 1 | Host PC | Host PC running Linux. (It is also possible to use Linux by building a virtual machine (VM) environment on a Windows PC.) This document describes a virtual machine environment built on Windows® 7 Professional using a combination of Oracle® VM VirtualBox (hereinafter referred to as VirtualBox) and CentOS 6.9 (hereinafter referred to as CentOS 6) to verify the operation. U-Boot compilation is only supported on Linux host machines. It is not supported on Windows. Please refer to the following website for how to build a virtual machine environment: Building a virtual machine environment with VirtualBox and CentOS 6 - (In Japanese) |
| 2 | Quartus® Prime Development Software Standard Edition (or Pro Edition) (hereafter Quartus® Prime) |
Tools for developing SoC FPGA hardware. This document uses Quartus® Prime Development Software Standard Edition v18.1. Quartus Prime Standard Edition v18.1 for Linux Quartus® Prime Pro Edition is required to actually compile the design file a10_soc_devkit_ghrd_qspi.tgz described in this document. You will need to install the Device data for the Intel® SoC FPGA on the target board you are using. For instructions on how to install the Quartus® Prime development software, please visit the following site: How to Install Intel® Quartus® Prime & ModelSim® - Intel® FPGA Edition (v18.0) - (In Japanese) |
| 3 | SoC FPGA Embedded Development Suite Standard Edition (hereafter SoC EDS) |
Tools for developing software for SoC FPGAs. |
| 4 | Arria® 10 SoC Development Kit | This is the development kit used as the target board in this document. It is used with the QSPI Boot Flash daughter card installed. Intel® Arria® 10 SX SoC Development Kit |
| 5 | QSPI Boot Contents for Arria® 10 SoC Development Kit | To actually verify the operation described in this document, download the following hardware design files along with this document: A10_SoC_DevKit_GHRD_QSPI.tgz The description in this document assumes that the above file downloaded is stored in /home/Student/Temp. GSRD tagging information ・ Arria 10 QSPI boot hardware (v17.1: a10_soc_devkit_ghrd_qspi.tar.gz) ・ Arria 10 QSPI boot precompiled binaries (v17.1: linux-socfpga-qspi-17.1-a10.tar.gz) |
| 6 | bare-metal sample applications | This is the bare-metal sample application used in this document. This bare-metal application is a simple application that displays a "Hello from Arria 10 SoC!!!" message via UART. If you actually want to check the operation, please obtain the following application file along with this document: ALT-HWLib-HelloWorld-Unhosted-A10-GNU.tgz The description in this document assumes that the above file downloaded is stored in /home/Student/Temp. |
| 7 | Terminal Emulation Software | Serial terminal software is required to use this sample. In this document, freeware software called "Tera Term" is used. URL to download Tera Term In Tera Term, make the following settings for the valid COM port when connecting to the UART on the target board. ・ Baud rate 115200 bps ・ 8 bits data ・ No parity ・ 1 stop bit ・ No flow control |
Point:
This document assumes a basic knowledge of Quartus® Prime development software, SoC FPGA Embedded Development Suite (SoC EDS), bsp-editor (2nd stage bootloader generator), and Arm® Development Studio 5 Intel® SoC FPGA Edition.
For reference:
The following user guide will help you with basic operations related to booting SoC FPGAs.
For QSPI boot information for SoC FPGAs, please refer to the following pages.
For basic operation of bare metal SoC FPGAs, please refer to the following user guide.
- Bare Metal User Guide UG-01165
- UG-01165: Bare Metal User Guide --> Errata - Intel
- SoC Beginner's Guide - Bare-metal Application Debugging with DS-5 - (In Japanese)
For information for SoC FPGA bare-metal developers, please refer to the following pages.
For free online training on SoC FPGA bare-metal programming and hardware libraries, please refer to the following pages.
- SoC Bare-metal Programming and Hardware Libraries - Intel " (English, 28 minutes)
2. Advance preparation
This document uses the Arria® 10 SoC FPGA Development Kit as an example target board.
This section describes the board configuration and hardware design files required to use the above board.
2-1. Board configuration
2-1-1. Board layout
The layout diagram of the Arria® 10 SoC Development Kit is shown below.
[Figure 2-1] Arria® 10 SoC Development Kit Layout Diagram
2-1-2. Power supply and cable connections
Connect the AC adapter and various cables as follows
- Attach the QSPI Boot Flash Daughter Card to the daughter card connector (J23).
- Connect the host PC to the On-Board USB-Blaster II connector (J22) with a Micro USB cable.
- Connect the host PC to the UART connector (J10) with a Mini USB cable.
- Connect the power supply (AC adapter) to the DC Input (J36).
2-1-3. BSEL (BOOTSEL) Pin Settings
By installing the QSPI Boot Flash Daughter Card in the Arria® 10 SoC Development Kit, the BSEL pin is set to QSPI boot. No jumpers or other settings related to BSEL are required.
Reference: For information on the Arria® 10 SoC Development Kit, please refer to the following document.
2-2. Hardware design files
In order to generate the 2nd stage boot loader described in "5. How to generate 2nd stage boot loader (U-Boot) for QSPI flash boot", the "handoff file" generated in hardware development is required.
2-2-1. Where to obtain hardware design files
To actually verify the operation described in this document, download and use the hardware design file A10_SoC_DevKit_GHRD_QSPI.tgz for QSPI boot for the Arria® 10 SoC Development Kit.
Please download it from the same page where you downloaded this document.
In the explanation of this document, it is assumed that the above file downloaded is stored in /home/Student/Temp.
2-2-2. Important deliverables in hardware developmentt (Handoff Files)
In developing and debugging bare-metal applications, the final folders and files generated during hardware development are used.
These folders and files are called "handoff files.
Handoff files contain FPGA hardware design information (as XML files) and are used to generate the bootloader device trees required for initialization and runtime access to the appropriate FPGA hardware.
If generated correctly, there are hardware software handoff files generated by the tool in the hps_isw_handoff folder. These files are used in section "5-2. 2nd stage boot loader generation procedure".
Please keep in mind that the bsp-editor (2nd stage bootloader generator) tool used to generate the 2nd stage bootloader will specify the path to this hps_isw_handoff folder.
2-3. Bare-metal sample application
You will need the sample application ALT-HWLib-HelloWorld-Unhosted-A10-GNU.tgz described in "4-2. Importing a bare-metal sample application".
Please download it from the same page where you downloaded this document.
In the explanation of this document, it is assumed that the downloaded file above is stored in /home/Student/Temp.
3. Boot flow of SoC FPGA
First of all, the boot flow of SoC FPGA is explained.
Reference: For more information on the boot flow, please refer to the following user guide.
As shown in the figure below, there are multiple stages in the SoC FPGA boot flow.
Most bare-metal applications use the 2nd stage bootloader (U-Boot / UEFI Bootloader), shown in red below, to directly boot the bare-metal application.
This document also describes the mechanism to achieve this bare-metal application boot flow.
[Figure 3-1] General Boot Flow
[Figure 3-2] Bare Metal Application Boot Flow
- BootROM
Boot ROM is the boot code burned into the SoC FPGA's built-in on-chip ROM (user modification is not allowed).
The Boot ROM code determines the boot source, initializes the hard processor system (HPS) after reset, and then jumps to the 2nd stage boot loader.
- 2nd Stage Boot Loader
Based on the information in the handoff file, the 2nd stage boot loader performs initialization and other processes necessary for operation.
An example of a 2nd stage boot loader in a typical boot flow is U-Boot.
Also, although not detailed in this document, the UEFI (Unified Extensible Firmware Interface) boot loader can be used as a non-GPL licensed boot loader source.
The 2nd stage boot loader can load an OS, bare-metal applications, etc.
- Bare-metal Applications
Applications that do not use an OS are called bare-metal applications. You can use the SoC FPGA hardware library (HWLib) to create bare-metal applications that read and write directly to the hardware.
4. How to build a bare-metal sample application on the DS-5
This chapter describes how to import and build a bare-metal sample application project into Arm® Development Studio 5 Intel® SoC FPGA Edition (DS-5).
4-1. Getting started with DS-5
Start Arm® Development Studio 5 Intel® SoC FPGA Edition, which is included in the SoC FPGA Embedded Development Suite.
To automatically configure the SoC FPGA environment, Arm® Development Studio 5 Intel® SoC FPGA Edition should be started from the Embedded Command Shell shown below.
4-1-1. Launching the Embedded Command Shell
Start the Embedded Command Shell by executing the startup script embedded_command_shell.sh, which is located under the SoC FPGA Embedded Development Suite installation folder (embedded folder).
[Figure 4-1] Launching Embedded Command Shell
4-1-2 Starting DS-5
(1)
When the Embedded Command Shell window opens as shown below, enter the command eclipse & to start DS-5.
[Figure 4-2] Starting DS-5
(2)
You will be prompted to enter a workspace folder. Select or create a unique workspace for your software project. Specify the path and click [OK] (in this example, the workspace is /home/Student/Work/DS-5_Workspace. If the folder does not exist, it will be created automatically).
[Figure 4-3] Specifying the workspace for DS-5
(3)
If the DS-5 Welcome Screen appears, click [Close] (marked with an X). The DS-5 Welcome Screen can be used to access documents, tutorials and videos.
[Figure 4-4] DS-5 Welcome Screen
4-2. Importing a bare-metal sample application
In this example, import the previously downloaded bare metal sample application ALT-HWLib-HelloWorld-Unhosted-A10-GNU into DS-5.
This bare-metal sample project has the following features.
- This is a simple application that only displays the "Hello from Arria 10 SoC!!!" message.
- The io.c file redirects the output of printf() to the UART, useful for standalone applications.
- The startup.s file adds a process to disable interrupts at the beginning of the application. This prevents the application from getting unexpected interrupts and detecting exceptions when interrupts are enabled for some peripherals in the U-Boot.
- Since loading Executable and Linkable Format (ELF) is an optional feature in U-Boot, the .axf (ELF) file is converted to a .bin (plain binary) file in the Makefile to generate hello.bin.
Note:
Since interrupts are enabled at U-Boot, it is necessary to disable interrupts when starting the bare-metal application.
Reference:
The following links are for Cyclone® V SoC FPGAs, but the concepts are similar.
SoC Beginner's Guide - Bare-metal Application Debugging with DS-5 - (In Japanese)
～ Example of bare-metal application standalone execution from SD card ～
(1)
Select "File" -> "Import..." from the DS-5 menu.
(2)
Select "General" -> "Existing Projects into Workspace" and click [Next>].
[Figure 4-5] Importing an existing project
(3)
Select the "Select archive file:" option, select ALT-HWLib-HelloWorld-Unhosted-A10-GNU.tgz from the "Browse..." button, and then click the "Finish" button.
Point:
The description in this document assumes that ALT-HWLib-HelloWorld-Unhosted-A10-GNU.tgz is stored in /home/Student/Temp.
[Figure 4-6] Selecting a sample application
(4)
The imported bare-metal sample application project ALT-HWLib-HelloWorld-Unhosted-A10-GNU is added to the Project Explorer panel on the left side of the DS-5 screen, and AlteALT-HWLib- HelloWorld-Unhosted-A10-GNU When expanded, the various files included in the project will be displayed.
[Figure 4-7] Project added by import
4-3. Build the bare-metal sample application
Next, the imported bare-metal sample application project is built and ready to run.
4-3-1. Build the Project
Highlight the DS-5 project (in this example, ALT-HWLib-HelloWorld-Unhosted-A10-GNU), right-click and execute "Build Project".
When the build is complete, a hello.bin file for the bare-metal application will be generated.
[Figure 4-8] Project Build
hello.bin is the bare-metal application image loaded by the 2nd stage boot loader (U-Boot).
Write this application image and the 2nd stage boot loader described in "5. How to generate 2nd stage boot loader (U-Boot) for QSPI flash boot" to the QSPI flash.
5. How to generate 2nd stage boot loader (U-Boot) for QSPI flash boot
This chapter describes the procedure for generating the 2nd stage bootloader required to boot bare-metal applications from QSPI flash on an Arria® 10 SoC.
5-1. What is a 2nd stage boot loader?
The 2nd stage boot loader is customizable and is typically stored in non-volatile flash-based memory external to the HPS or in on-chip RAM within the FPGA.
The 2nd stage boot loader can load the OS, bare-metal applications, or the 3rd stage boot loader.
Examples of 2nd stage boot loaders are the U-Boot and UEFI (Unified Extensible Firmware Interface) boot loaders.
(1)
Intel provides the following 2nd stage boot loader roles.
- Configure HPS pin multiplexing
- HPS IOCSR configuration
- HPS PLL and clock settings
- Unreset HPS peripherals
- Initialize SDRAM (e.g., calibration)
- Next stage program deployment/jump to SDRAM
(2)
UEFI boot loader can also be used as a non-GPL licensed boot loader source. UEFI replaces the MPL boot loader in Cyclone® V and Arria® V devices. The UEFI boot flow runs entirely in the HPS on-chip memory and is the default choice for booting bare-metal applications and RTOS.
Point:
This document describes an example using U-Boot primarily as the 2nd stage boot loader.
For more information on UEFI boot loaders, please refer to the Intel® Arria® 10 SoC UEFI Boot Loader User Guide.
(3)
The 2nd stage boot loader is automatically generated by using a handoff file that is automatically generated during design in Quartus® Prime development software/platform designer. Therefore, the user can reflect the settings made in Quartus® Prime development software/platform designer to the HPS block without having to build the initialization software.
(4)
The 2nd stage boot loader must be generated first to run the custom board with the user's SoC FPGA.
5-2. 2nd stage boot loader generation procedure
The procedure for generating the 2nd stage bootloader is described below.
The SoC FPGA Embedded Development Suite includes a 2nd Stage Boot Loader Support Package (BSP) generator tool that enables you to generate a boot loader for your FPGA design.
Use this tool to configure and generate the 2nd stage bootloader.
5-2-1. Launching Embedded Command Shell
Follow the same procedure as described in section "4-1-1. Starting Embedded Command Shell".
Execute the startup script embedded_command_shell.sh stored in the SoC FPGA Embedded Development Suite installation folder (embedded folder) to start the Embedded Command Shell.
5-2-2. Extracting hardware design file
In this document, it is assumed that the downloaded hardware design file A10_SoC_DevKit_GHRD_QSPI.tgz is stored in /home/Student/Temp.
Enter the following command from the Embedded Command Shell to extract the file A10_SoC_DevKit_GHRD_QSPI.tgz.
[Figure 5-1] Extracting the Hardware Design File
5-2-3. Start bsp-editor (2nd stage boot loader generator)
When the Embedded Command Shell window opens as shown below, enter the command bsp-editor to launch the bsp-editor (2nd stage boot loader generator) GUI.
[Figure 5-2] Launching bsp-editor (2nd stage boot loader generator)
5-2-4. Create a new bsp project
After the bsp-editor GUI starts up as shown in the figure, select "File" -> "New HPS BSP..." from the menu to create a new project.
[Figure 5-3] Creating a new bsp project
5-2-5. Specifying a handoff file
(1)
Specify the handoff file folder path <Quartus Prime project>/hps_isw_handoff generated by
hardware development. Press [ ... ] in the "Preloader settings directory:" sequence to specify the folder, as shown in the figure.
For the purposes of this document, specify the following path.
/home/Student/Temp/A10_SoC_DevKit_GHRD_QSPI/hps_isw_handoff
(2)
Select U-Boot Bootloader (Arria 10 HPS) for "Operating system:".
(3)
After all specifications are complete, click [OK].
[Figure 5-4] Specifying the handoff file
5-2-6. Setting 2nd stage boot loader options
In the Main menu tab of the BSP Editor window, specify Boot from QSPI for "boot_device:".
[Figure 5-5] 2nd stage boot loader option settings
5-2-7. Generate bsp project (Generate)
Click the Generate button at the lower right to generate a bsp project.
The generated bsp project will contain the files necessary to generate (build) the 2nd stage boot loader, including *.c, *.h, and Makefile.
These files are generated in the location specified for the BSP target directory in section "5-2-5. Specifying a handoff files". In the example in this manual, they are generated in the following location.
/home/Student/Temp/A10_SoC_DevKit_GHRD_QSPI/software/uboot_bsp
After confirming that generation is complete, click the [Exit] button to exit bsp-editor.
[Figure 5-6] bsp project generation
5-2-8. Building the 2nd stage boot loader
(1)
Move the current directory of Embedded Command Shell to the directory of the bsp project created by bsp-editor. Enter the following command from Embedded Command Shell.
In the description of this document, the following directory is moved
/home/Student/Temp/A10_SoC_DevKit_GHRD_QSPI/software/uboot_bsp
[Figure 5-7] Move to the bsp project directory.
(2) Execute
Execute the make all command to generate the 2nd stage boot loader. Confirm that uboot_w_dtb-mkpimage.bin is generated by ls command. This file is a binary file with header information for the 2nd stage boot loader referenced by BootROM, and is the file to be written to QSPI flash.
[Figure 5-8] Execute the make all command
(3)
Even if the uboot_w_dtb-mkpimage.bin generated at this point is written to the QSPI flash, it is not possible to execute bare-metal applications standalone from the QSPI flash.
Loading and booting with U-Boot is command-based.
It is common practice to have an environment variable that automates this, and for the Arria® 10 SoC this is defined in the following file in the generated uboot-socfpga directory.
/A10_SoC_DevKit_GHRD_QSPI/software/uboot_bsp/uboot-socfpga/include/configs/socfpga_arria10.h
For example, if QSPI is selected, the default command consists of the following four commands (environment variables)
・ run qspirbfcore_rbf_prog
・ run qspiload
・ run set_initswstate
・ run qspiboot
The following environment variables are defined as entities.
[Figure 5-9] Entities of QSPI environment variables
As described above, it is described by command and assumes loading and booting of Linux Kernel by default.
(4)
Change the entity part of this QSPI environment variable to match the storage location of the bare-metal application you have created, the deployment location on DDR, etc., and use the go command instead of bootz to jump directly to the entry point.
Open the socfpga_arria10.h file by entering the following command from the Embedded Command Shell.
For the purposes of this document, we will modify two lines as follows to make the bare-metal application run standalone from the QSPI flash.
[Figure 5-10] Modification of QSPI environment variables for stand-alone execution of bare-metal applications
(5)
When you have finished modifying the socfpga_arria10.h file, save and close the file.
(6)
Enter the following command from Embedded Command Shell to regenerate the 2nd stage boot loader reflecting the above changes.
[Figure 5-11] Generated 2nd stage boot loader
Confirm that uboot_w_dtb-mkpimage.bin has been generated.
Follow the instructions in the next section to write this file to the QSPI flash to enable stand-alone execution of the bare-metal application.
6. Example of running a bare-metal application standalone from QSPI Flash
This chapter describes the steps necessary to enable standalone execution of a bare-metal application from the QSPI flash.
6-1. Layout of qspi flash
The following figure shows the QSPI flash layout in detail. Items of note in the diagram include.
- Normally, the 2nd stage boot loader (U-Boot) is written to boot loader images 0, 1, 2, and 3. For the purposes of this manual, only the 2nd stage boot loader image uboot_w_dtb-mkpimage.bin is written to boot loader image 0 (address 0x0).
- Write the next boot image (either a zImage, RTOS binary image, or bare-metal application binary image) to location 0x120000. For the purposes of this document, the bare-metal application binary image hello.bin is written.
- Writes the hardware design (Peripheral RBF) at 0x720000. The instructions in this document write the existing hardware design ghrd_10as066n2.periph.rbf.mkimage.
[Figure 6-1] Layout of QSPI Flash
Note:
Writing to the QSPI flash requires a connection via an Intel® FPGA download cable (USB-Blaster II).
If you are using USB-Blaster II for the first time with RedHat Linux Enterprise 5 or later, you will need to setup the USB-Blaster II driver.
Please refer to "7. Appendix: Setting up the Intel® FPGA download cable II with RedHat Linux Enterprise 5 or later" for the setup procedure.
6-2. Confirmation of QSPI Boot Flash daughter card installation
Verify that the Arria® 10 SoC Development Kit is equipped with a QSPI Boot Flash daughter card and capable of QSPI booting, as described in section "2-1-3. BSEL (BOOTSEL) Pin Settings".
6-3. How to write hardware design to QSPI Flash
To write to QSPI flash, use the HPS flash programmer utility.
The HPS flash programmer can erase, blank check, program, verify, and inspect the flash.
The following is the command line syntax for the HPS flash programmer:
quartus_hps <options> <file.bin>
The instructions in this document write the existing hardware design ghrd_10as066n2.periph.rbf.mkimage to QSPI flash.
Enter the following command from the Embedded Command Shell.
[Figure 6-2] Example of a successful hardware design write
6-4. How to write the 2nd stage boot loader and application image to the QSPI flash
Execute the following command from Embedded Command Shell to write the 2nd stage boot loader uboot_w_dtb-mkpimage.bin to the QSPI flash.
[Figure 6-3] Example of a successful writing of 2nd stage boot loader
Similarly, write the bare-metal application hello.bin to the QSPI flash.
[Figure 6-4] Example of a successful writing of bare metal application
6-5. Confirmation of standalone execution
Turn the board back on or reset the HPS by pressing the COLD Reset button (S2).
After the board boots and the 2nd stage bootloader message appears on the PC serial terminal, "Hello from Arria 10 SoC!!!" is displayed by the bare-metal application.
[Figure 6-5] Booting from QSPI Flash
Reference:
For more information on the SoC FPGA Embedded Development Suite, Arm® Development Studio 5 Intel® SoC FPGA Edition, the Preloader Generator, and the HPS Flash Programmer Utility, see the following user guides.
Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide ug-1137
7. Appendix: Setting up the Intel® FPGA download cable II with RedHat Linux Enterprise 5 or later
If you are using the Intel® FPGA download cable II (USB-Blaster II) with RedHat Linux Enterprise 5 or later for the first time, you will need to setup the USB-Blaster II driver. Please follow the steps below to complete the setup.
(1)
Execute the following command from Embedded Command Shell to create the file /etc/udev/rules.d/51-usbblaster.rules and write the following line.
[Figure 7-1] Contents to be written in the 51-usbblaster.rules file
(2)
Save and close the 51-usbblaster.rules file after completing the description.
(3)
Start Quartus® Prime and launch Programmer.
[Figure 7-2] Start Programmer.
(4)
After Programmer starts, click [Hardware Setup...]
[Figure 7-3] Click [Hardware Setup...]
(5)
When the Hardware Setup window opens, select USB-Blaster II from the Currently selected hardware: pull-down on the Hardware Settings tab, and click Close.
[Figure 7-4] Select USB-Blaster II from the pull-down menu and click [Close]
(6)
Return to the Programmer window and confirm that USB-Blaster II is configured. If the settings are correct, close the Programmer window.
[Figure 7-5] Confirm that USB-Blaster II is set
(7)
Enable the USB-Blaster II connection from the USB settings of Virtual Box.
[Figure 7-6] Enable USB-Blaster II connection from the Virtual Box USB settings
Documentation/Sample Projects
SoCFPGA_Baremetal_QSPI_Boot_A10_v181_r2.pdf - (In Japanese)
Instructional Material for Arria® 10 SoC Development Kit ver18.1 (rev.2)
ALT-HWLib-HelloWorld-Unhosted-A10-GNU.tgz
Bare Metal Sample Application
A10_SoC_DevKit_GHRD_QSPI.tgz
QSPI boot contents for Arria® 10 SoC Development Kit