Introduction.
This is an example of timing constraints for a system connection that latches with data synchronous clock.
SDC is a reasonable constraint to set considering the system configuration, RTL, and your specifications, so please do not copy the SDC in this example, but refer to it only as a support for your understanding.
System Configuration and Sample Circuit
This example shows an example of set_input_delay with the Port of DATAIN_50M of FPGA as Target in the case of the system connection as shown in the figure below.
SDC Constraints
An example of timing constraints without any consideration of on-board delays is shown below.
Clock constraint to synchronize the first stage FF (Latch Clock)
create_clock -name CLK_50M -period 20.000 [get_ports {CLK_50M}]]
Virtual clock constraint to synchronize the FF of the transmitting device (Launch Clock)
create_clock -name CLK_50M_vir -period 20.000
set_input_delay constraint for Port of DATAIN
set_input_delay -clock { CLK_50M_vir } -max -add_delay 3.000 [get_ports {DATAIN}]]
set_input_delay -clock { CLK_50M_vir } -min -add_delay 1.000 [get_ports {DATAIN}].
Report Timing
After compiling with timing constraints, use Timing Analyzer to check the results against the constraints by the following steps:
Create a netlist for timing analysis in Timing Analyzer .
Open the Report Timing setting screen,
Open the Report Timing Settings screen and set the SDC results to be reported as shown in the figure below (Figure 4).
In the setup analysis of Report Timing, the value set by -max is taken into account.
In the hold analysis of Report Timing, the value set by -min is taken into account.
This completes the Input constraints and checks when latching with a synchronous clock.
Please refer to the above for reference.