Introduction
The Stratix® 10 MX FPGA has two DRAMs (HBM2) in the package, one on the top side and one on the bottom side, to achieve a total memory bandwidth of 512GB/s, up to 256GB/s each.
The Quartus® Prime development software can generate example designs for simulation and production use to verify HBM2 operation.
This article describes the procedure for generating an Example Design and running simulations using the HBM2 controller IP core.
This article is presented in the following environment
- Quartus®Prime Development Software Pro Edition: Version 19.1
- ModelSim FPGA Edition 10.6d (Quartus Prime Pro 19.1)
- Language: Verilog
About Example Design
The block structure of the generated Example Design for simulation is shown in the figure below.
In addition to the HBM2 controller IP core, the HBM2 IP Memory Model and the Traffic Generator that controls the controller are generated.
The HBM2 IP core has two Pseudo Channels per channel and a Traffic Generator is generated for each Pseudo Channel.
Project Generation
First, start the Quartus®Prime development software and create a project.
Note that the device selection should be based on the MX family with HBM2.
How to Generate an Example Design
After generating the project, select High Bandwidth Memory (HBM2) Interface IP in the IP Catalog. After selecting, click "+ Add" (or double-click).
Enter a name for the core (in this case, "hbm2_core") and click Create.
Then, set each parameter of the core.
For details of the parameters, please refer to the following.
4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface IP
Parameterizing the High Bandwidth Memory (HBM2) Interface IP
The General tab allows you to configure the HBM2, number of channels, clock frequency, and other settings.
The Controller tab allows you to configure the controller settings and AXI interface settings.
In the Diagnostics tab, settings such as Traffic Generator and Efficiency Monitor to be generated are configured.
In the Example Designs tab, configure the settings for the generated Example Designs.
After setting, click "Generate Example Designs..." in the upper right corner. in the upper right corner of the screen.
This will generate an Example Design.
Simulation Procedure
The following is the procedure for running a logic simulation using ModelSim.
Start ModelSim and go to the following folder in the Change Directory.
In the Transcript window, type "do msom_setup.tcl".
In the Transcript window, type "ld_debug".
In the Transcript window, type "log -r /*". This will log all signals.
In this case, the procedure is to add the signals to the wave window after the simulation is run.
In the Transcript window, type "run -all".
After running the simulation, enter "add wave -radix hexadecimal *" in the Transcript window.
This will add all signals in the top level to the wave window in hexadecimal format.
This will display the simulation waveforms on the wave screen.
You will see that "sim_traffic_gen_pass = 1" is set near 16.4 us.
The generated testbench will now stop simulation.
The I/F waveform with HBM2 memory is shown below.
AXI I/F waveform is shown below.
For details of the logical simulation execution procedure, please refer to the following.
5. Simulating the High Bandwidth Memory (HBM2) Interface IP
Simulating the High Bandwidth Memory (HBM2) Interface IP
Summary
This article introduced the simulation procedure for the HBM2 IP core Example Design.
Please use it to confirm the operation.
Reference Documents
This article refers to the following documents.
HBM2 IP Core User Guide:
High Bandwidth Memory (HBM2) Interface IP User Guide
HBM2 IP Core Example Design User Guide:
High Bandwidth Memory (HBM2) Interface IP Design Example User Guide