Nios® II Boot Option ~ CFI Flash ~

1. Overview (Configuration diagram including IPs)

This content describes how to set minimum necessary IP parameters, BSP Editor settings, and generate various files to boot a Nios^® II processor from CFI Flash with Boot Copier or XIP.

Please refer to the following contents for the difference between XIP and Boot Copier.

Reference: Configuration of Nios^® II Boot and settings for each Boot Option

CFI Flash is typically used with the Fast Passive Parallel (FPP) configuration scheme. Many Development kit, for example, use the FPP configuration scheme to provice access to CFI Flash using an FPGA device with a Parallel Flash Loader (PFL) IP capable of control the FPP configuration.
On the other hand, Nios^® II uses the Avalon Tri-State Conduit Component to access the CFI Flash.

Please refer to the following user guide from the manufacturer for configuration and detailed explanation.

Reference: Embedded Design Handbook -> 5.2.6. Nios II Processor Booting from CFI Flash

The Avalon Tri-State Conduit Component used to access the CFI Flash from the Nios^® II is an IP with the following capabilities:

• Generic Tri-State Controller
  Parameters can be set to control a variety of flash devices.
• Tri-State Conduit Bridge
  Converts Tri-State Slave signals to bi-directional signals that connect to flash devices on the board.
• Tri-State Conduit Pin Sharer
  Provides unified access to input and output signals when there are multiple controllers.
  (Tri-State Conduit Pin Sharer is not used in this content)

For information on the Avalon Tri-State Conduit Component, please refer to this content.

Reference: How to connect off-chip memory interface in Qsys - (In Japanese)

Reference: Avalon Tri-state Conduit Components User Guide

The minimum IP requirements are as follows (Intel^® Quartus^® Prime development software ver 18.1).

• Nios^® II Processor
• On-Chip Memory (RAM or ROM) Intel^® FPGA IP: Execution Memory
• Generic Tri-State Controller
• Tri-State Conduit Bridge

Figure 1 shows an example of the Platform Designer configuration.

[Figure 1] Platform Designer configuration example

1-1. Nios^® II Processor

Set Reset Vector / Exception Vector.
The setting differs depending on whether the XIP or Boot Copier method is used. Please refer to the following.

"2. Nios^® II settings for execution from CFI Flash with XIP"
"3. Nios^® II settings for execution from CFI Flash with Boot Copier"

1-2. On-Chip Memory (RAM or ROM) Intel^® FPGA IP

Set the Total Memory Size required for software execution as shown in Figure 2.

[Figure 2] On-Chip Memory parameter setting example

1-3. Generic Tri-State Controller parameter settings

Please also refer to the following contents.

Reference: How to connect off-chip memory interface in Qsys - (In Japanese)

Select Flash Memory Interface (CFI) from the Library and press Apply.
Refer to the datasheet of your CFI Flash device and confirm that the various parameters are correct. Also, check that the settings on the various tabs are as shown below.

1. In the Signal Selection tab, check that the following items are set correctly according to the CFI Flash specifications
   ・Address width
   ・Data width
   ・Byteenable width
   ・Bytes per word
   
   ・readdata
   ・writedata
   ・read
   ・write
   ・chipselect
   ・address
   
   
2. Check if Signal Timing meets CFI Flash specifications
   
   
3. In the Signal Polarities tab, check that the following signals and settings are enabled
   ・read
   ・write
   ・chipselect
   
   
4. Check if Is memory device in Parameters is enabled.
   
   
5. Check that Module Assignments is set to the following
   ・embeddedsw.configuration.hwClassnameDriverSupportList
     : altera_avalon_lan91c111:altera_avalon_cfi _flash
   ・embeddedsw.configuration.whClassnameDriverSupportDefault
     : altera_avalon_cfi_flash
   
   
6. Confirm that Avalon Connection Point Assignments is set as follows
   ・Embeddedsw.configuration.isFlash: 1 Value
   ・Embeddedsw.configuration.isMemoryDevice: 1 Value
   ・Embeddedsw.configuration.isNonVolatileStorae: 1 Value

[Figure 3] Generic Tri-State Controller configuration example

After the system configuration of Platform Designer is completed, use Generate HDL to generate.

1-4. Quartus^®  Prime Settings

This setting has no effect on the boot of Nios^® II Processor, but if FPP is used, it should be set the Configuration Scheme to Passive Parallel x8 / x16 / x32 in Quartus^® Prime under Assignments -> Device -> Device and Pin Options -> Configuration.

[Figure 4] Quartus^® Prime Settings

Set the Platform Designer to Quartus^® Prime project and compile it to generate SOF files when development is finished.

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2. Nios^® II settings for execution from CFI Flash with XIP

Explains the Reset Vector / Exception Vector settings and BSP Editor settings for the Nios^® II Processor.

The Boot method of the XIP is to use the Nios^® II Processor on the CFI Flash, it is an effective configuration for systems that do not have enough On-Chip RAM. However, the processing speed is lower than the Boot Copier configuration.
.rodata, .rwdata, .exceptions, etc. are copied onto RAM using the alt_load() function. The main software, .text, remains on the CFI Flash and Nios^® II is executed on the CFI Flash.

Hardware breakpoints are required to debug the XIP configuration, and the method is introduced in the following contents.

Reference: How to use Run/Debug Configuration settings in Nios^® II SBT for Eclipse - (In Japanese)

2-1. Parameter settings for Nios^® II Processor in XIP configuration

When booting Nios^® II with XIP, there are two Vector settings for the Nios^® II Processor.

1. Reset Vector and Exception Vector are both set to Generic Tri-State Controller.
2. Set Generic Tri-State Controller for Reset Vector and On-Chip RAM or external RAM for Exception Vector.

[Figure 5] Nios^® II Vectors setting in XIP configuration

Setting RAM for the Exception Vector allows exception handling to run faster than with Flash, which can improve Nios^® II performance.

<How to set Reset Vector offset>

The Reset Vector Offset must be set to match the location of the Nios^® II software to be stored in the CFI Flash. According to the user guide of the Arria^® V GX Starter Kit used for checking the operation, the User_software area is 0x0528_0000 ~ 0x07FD_0000, so 0x05280000 is set as shown in Figure 5.

Reference: Arria V GX Starter Kit User Guide

Once the various Platform Designer settings has been completed, run Generate to compile Quartus^® Prime and generate the SOF file.

2-2. BSP Editor settings for Nios^® II SBT in XIP configuration

Start the Nios^® II SBT and generate Application and BSP.
Start BSP Editor and set Linker Script and alt_load() function options.

Set the Linker Script as shown in Figure 6.
Set the .text section to Generic Tri-State Controller, and set other sections to On-Chip RAM or external RAM.

[Figure 6] Linker Script settings in XIP configuration

In the Main tab, under Settings -> Advanced -> hal -> linker, set the alt_load() function options as shown in Figure 7.
The setting items differ depending on the two types of Nios^® II Processor Vectors settings described above.

[Figure 7] alt_load() function setting for XIP configuration

This completes the various settings to realize the XIP configuration.
The next step is to generate the HEX and Programming file for the CFI Flash, see section 4.

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3. Nios^® II settings for execution from CFI Flash with Boot Copier

Explains the Reset Vector / Exception Vector settings and BSP Editor settings for the Nios^® II Processor.

The Nios^® II Boot method in the Boot Copier is described below.

Reference: 3-2. Boot Format 2 - Other Controller Support (Current) - (In Japanese)

3-1. Parameter settings for Nios^® II Processor in Boot Copier configuration

When booting the Nios^® II with Boot Copier, the Nios^® II Processor has only one Vectors setting.

1. Set the Reset Vector to Generic Tri-State Controller and the Exception Vector to On-Chip RAM or external RAM.

[Figure 8] Nios^® II Vectors settings in Boot Copier configuration

<How to set Reset Vector offset>

The Reset Vector Offset must be set to match the location of the Nios^® II software to be stored in the CFI Flash. According to the user guide of the Arria^® V GX Starter Kit used for checking the operation, the User_software area is 0x0528_0000 ~ 0x07FD_0000, so 0x05280000 is set as shown in Figure 8.

Reference: Arria V GX Starter Kit User Guide

Once the various Platform Designer settings has been completed, run Generate to compile Quartus^® Prime and generate the SOF file.

3-2. BSP Editor Settings for Nios^® II SBT in Boot Copier configuration

Start the Nios^® II SBT and generate Application and BSP.
Start BSP Editor and set Linker Script and alt_load() function options.

Set the Linker Script as shown in Figure 9.
Set the .text section to On-Chip RAM or external RAM, and set other sections to On-Chip RAM or external RAM.

[Figure 9] Linker Script settings in Boot Copier configuration

Then, set the alt_load() function options in the Settings -> Advanced -> hal -> linker item in the Main tab as shown in Figure 10.

The Boot Copier configuration does not use alt_load(), so remove all check boxes.

[Figure 10] alt_load() function settings for Boot Copier configuration

This completes the various settings to realize the Boot Copier configuration.
After writing the SOF file to the FPGA and verifying that the software works correctly with the "Run As" of the Nios^® II SBT, the next step is to generate the HEX file and Programming file to be stored in the CFI Flash, see section 4.

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4. How to generate the Programming File

After the software has been compiled by Nios^® II SBT and the ELF file has been generated, the next step is to generate the FLASH file or the HEX file. The required file differs depending on the method of writing.

4-1. Generation of FLASH and HEX file

Once the ELF file has been generated, right-click on the Nios^® II application as shown in Figure 11 and use Make Targets -> Build... -> mem_init_generate Generate -> Build to generate the FLASH file.

When using "5-1. How to write using the quartus_pgm -nios2 command", use the generated FLASH file.

[Figure 11] mem_init_generate for HEX

There are three main types of files generated by mem_init_generate.

• meminit.qip: Used by registering to the project when booting from On Chip RAM
• on_chip_ram.hex: Used as the initial value file of RAM when booting from On Chip RAM
• <Flash_Controller_Name>.flash: Software file to store CFI Flash
  (Created under Project)

If you use "5-2. Writing with Quartus^® Programmer via FPGA with built-in PFL", you need to generate POF file. When storing in POF file, the FLASH file must be converted to a HEX file. Lunch the Nios^® II Command Shell and use the following command to convert to a HEX file.
In the Nios^® II SBT, right-click Application and press Nios^® II -> Nios^® II Command Shell to lunch the Nios^® II Command Shell with the Application folder path.

nios2-elf-objcopy --input-target srec --output-target ihex CFI_Flash_Controller.flash CFI_Flash_Controller.hex --verbose 

[Figure 12] Converting from a FLASH file to a HEX file

4-2. Generating the POF file

When using "5-2. Writing with Quartus^® Programmer via FPGA with built-in PFL",

Generate a POF file with a HEX file at the address of the CFI Flash you want to store.
If you also want to store Configuration Data, add a SOF file.

For details, please refer to the following user guide from the manufacturer.

Reference: Embedded Design Handbook -> 5.2.6.2.3. Programming

According to the user guide of the Arria^® V GX Starter Kit used for checking the operation, the User_software area is 0x0528_0000 ~ 0x07FD_0000, so use the Convert Programming File to create it as shown in Figure 13.

Reference: Arria V GX Starter Kit User Guide

[Figure 13] Convert Programming File at POF generation

By preparing an FPGA design that has a built-in PFL with the Programmer setting, the POF can be written to the CFI Flash.

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5. How to write to CFI Flash

5-1. How to write using the quartus_pgm -nios2 command

Start the Nios^® II Commad Shell.

Go to the path where the SOF file is saved and execute the following command to write the SOF of the design to be used into the FPGA (Quartus^® Programmer can also write SOF).

quartus_pgm.exe -c 1 -m jtag -o "P;CFI_Nios_boot.sof@1"

Go to the path where the Flash file is saved and the following command can be used to write Nios^® II software to the CFI Flash.

quartus_pgm.exe --nios2 --base=0x00000000 CFI_Flash_Controller.flash --debug

--base: Base address of Generic Tri-state Controller as seen by Nios^® II software in Platform Designer
--debug: Log contents will increase if given

To erase the Nios^® II software area, execute the following command.

quartus_pgm.exe --nios2 --base=0x00000000 --erase=0x05280000,0x02d60000

--erase: =<Sector address to erase, capacity to erase> (For CFI Flash, specify the capacity to erase)

For details of the command, refer to the manufacturer's user guide below.

Reference: Nios^® II Flash Programmer User Guide

5-2. Writing with Quartus^® Programmer via FPGA with built-in PFL

To write, a design connected to CFI Flsah that includes PFL in the Programmer settings is required.

For detailed writing procedures, please refer to the following user guide from the manufacturer.

Reference: Embedded Design Handbook -> 5.2.6.2.3. Programming

Recommendation Page

We have prepared a "Nios^® II Summary Page - (In Japanese)" that summarizes various information on Nios^® II. Please refer to this page as well, as it is full of useful information other than this article.