Introduction.
Intel® FPGAs provide programmable delay elements within the IO block (called IO Element) of the device.
Normally, you would use an SDC file to set the timing for the input and output pins, and when Quartus compiles the device, it will automatically adjust the timing using the delay elements as needed.
However, these delay elements can also be set manually as desired.
In this article, we will introduce how to manually set these delay elements.
Structure of the FPGA IO Block (IOE)
This section describes how to configure the programmable delay elements of the Cyclone IV E FPGA.
Below is the IOE structure of the Cyclone IV E FPGA.
In the above figure
"Output Pin Delay"
"Input Pin to Input Register Delay or Input Pin to Logic Arrey Delay"
block is the programmable delay element and you can set the delay in this block.
How to set the Input Pin Delay
There are two types of Input Pin Delay.
① Input Pin to Input Register Delay
- Programmable delay element that is enabled when DFF in IOE is used (resolution 8)
② Input Pin to Logic Arrey Delay
- Programmable delay element (resolution 7) that is enabled when DFF in IOE is not used.
*Delay value by resolution depends on pin location and device type, please refer to the following document "IOE Programmable Delay" at
The settings are made in the Quartus® Assignment Editor.
(Select Assignment Editor from the Quartus® Assignment menu.)
Input pin name in the "To" column,
In the "Assignment Name" column, select "Input Delay from Pin to Input Register" for ①,
Select "Input Delay from Pin to Internal Cells" for ②,
In the "Value" column, Enter any number in the "Value" field.
The following is an example of setting "Input Delay from Pin to Input Register" to 5.
Run compilation on Quartus® and confirm that the set values are valid.
You can check the value in the Fitter -> Resource Section -> Delay Chain Summary in the compilation report.
How to set Output Pin Delay
The Output Delay setting is also made in the Quartus® Assignment Editor.
(Select Assignment Editor from the Quartus® Assignment menu.)
The resolution of the Output Pin Delay setting is 2.
For the Output Pin Delay setting, DFF in IOE must be used.
The delay value by resolution depends on the pin location and device type.
Please refer to the following document "IOE Programmable Delay" section.
Select the output pin name in the "To" column,
"Delay from Output Register to Output Pin" in the "Assignment Name" column, and
any number in the "Value" column.
The following is an example when "Delay from Output Register to Putput Pin" is set to 1.
You can check the value in the Fitter -> Resource Section -> Delay Chain Summary in the compilation report.