How to simulate the entire project including Nios® II

1. Overview

In this article, we will introduce how to simulate the operation of Nios^® II software along with user logic modules registered on the Quartus^® Prime side, without registering them in Platform Designer (formerly Qsys). In other words, we will explain how to simulate the entire Quartus^® Prime project that includes Nios^® II.

For a simpler method to verify the operation of Nios II software using only Platform Designer blocks in simulation, please refer to the content below.

[Reference contents] 
Nios^® II Beginner's Guide - Nios^® II Simple Simulation - (In Japanese)

The following tools are used in this article.

・Quartus^® Prime Standard Edition ver 18.1 (hereafter, "Quartus^® Prime"  will be used) 
・ModelSim^® -Altera^® FPGA Edition 10.5b (hereafter, "ModelSim^®" will be used)

*Caution 
The simulation methodology described in this article is based on the Nois^® II Boot configuration is assumed to be Boot from On Chip RAM.

2. Simulation Procedure

First, it is assumed that the following have been completed.

・Various designs of Quartus^® Prime 
・Platform Designer configuration 
・Software to run on Nios® II 
・Test bench to be used for simulation

2-1 Preparation

When generating the platform designer, the simulation model of the platform designer is generated together. Configure the settings as shown in Figure 1 and click Generate. 
Confirm that the simulation folder is generated under the generated folder of the platform designer.

[Figure 1] Generate in Platform Designer

Nios^® II Software Build Tools for Eclipse (hereafter, "Nios^® II SBT" will be used) to generate a HEX file of the software.

As shown in Figure 2,

Right click on the application → Make Targets → Build... → mem_init_generate → Build

Generate the ***_onchip_memory.hex file. 
You will see the HEX file generated in the mem_init folder under the application folder.

[Figure 2] Generating the HEX file

2-2 Storing the HEX (software file)

By storing the generated ***_onchip_memory.hex file in the folder where the simulation model used in the simulation is stored, the Nios^® II simulation as shown in the software file.

Swap the default ***_onchip_memory.hex file, located in <Quartus project>/<Platform Designer folder>/simulation/submodule, and the ***_onchip_memory.hex file generated in 2-1, as shown in Figure 3.

[Figure 3] Storing the HEX file

2-3 Customizing msim_setup.tcl

The script file (msim_setup.tcl ) for setting up the files generated by the platform designer and the required simulation models in ModelSim^® is available in the following folder.

<Quartus project>/<Platform Designer folder>/simulation/mentor/msim_setup.tcl

In this case, we will introduce an example of msim_setup.tcl customization using a platform designer system (nios2_system) containing Nios^® II and a design containing user circuits (led7) as shown in Figure 4.

[Figure 4] Example Design

Add commands to compile the user circuit HDL and testbench in the design compilation description of msim_setup.tcl as shown in Figure 5.

[Figure 5] msim_setup.tcl compile command description

 vlog -reportprogress 300 -work work E:/Work/Emb_study/NiosII_Simulation/sim_again_ver1/nios2_basic_lab.v 
 vlog -reportprogress 300 -work work E:/Work/Emb_study/NiosII_Simulation/sim_again_ver1/led7.v 
 vlog -reportprogress 300 -work work E:/Work/Emb_study/NiosII_Simulation/sim_again_ver1/simulation/modelsim/nios2_basic_lab.vt

msim_setup.tcl custom example in Figure 5

Modify the load simulation command (vsim) as shown in Figure 6. 
Modify and add to the description in elab_debug. 
In the default load simulation command, it is set to "$TOP_LEVEL_NAME", but since this is not the testbench module name being used, it should be modified to the module name being used. (There is a description defining "TOP_LEVEL_NAME" at the beginning of the file, so you can also modify it.)

In addition, if you add a command to add the signal you want to see to the wave screen (add wave) and a command to run the simulation (run), you can automatically display the waveforms.

[Figure 6] msim_setup.tcl load simulation command description

# Elaborate the top level design with novopt option
alias elab_debug {
 echo "\[exec\] elab_debug"
 eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux_001 -L rsp_demux -L cmd_mux_001 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L nios2_gen2_0_data_master_limiter -L router_003 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L nios2_gen2_0_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L nios2_gen2_0_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L pio_SW -L onchip_memory -L nios2_gen2_0 -L led_pio -L jtag_uart -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver nios2_basic_lab_vlg_tst
 add wave -position end sim:/nios2_basic_lab_vlg_tst/*
 add wave -position end sim:/nios2_basic_lab_vlg_tst/i1/u0/jtag_uart/av_writedata
 add wave -position end sim:/nios2_basic_lab_vlg_tst/i1/u0/led_pio/data_out
 run -all
}

msim_setup.tcl custom example in Figure 6

For more information on how to read the ModelSim^® script file and the commands used, see the following article.

[Reference content] 
How to function and simulate in ModelSim a design containing IP generated by Quartus® Prime Pro Edition - (In Japanese)

2-4 Running Simulations with ModelSim^®

Start up ModelSim^® and go to the directory where msim_setup.tcl edited in 2-3 is saved from File menu → Change Directory. (Figure 7) 
Tools → Tcl → Execute Macro... Select msim_setup.tcl and execute it.

[Figure 7] Executing msim_setup.tcl in ModelSim^®

When msim_setup.tcl is executed, it will pause and a menu will appear in Transcript as shown in Figure 8. 
When you enter "ld_debug", the compilation and simulation of various files will be executed.

[Figure 8] Execution of ld_debug

When the execution finishes to the end, the waveform is displayed as shown in Figure 9, and you can confirm the completion of the simulation for Nios^® II and other HDL modules.

[Figure 9] Confirmation of waveform display

Recommendation Page

We have prepared a "Nios^® II Summary Page - (In Japanese)" that summarizes various information on Nios^® II. Please refer to this page as well, as it contains a lot of useful information in addition to this article.

• Nios^® II Summary Page - (In Japanese)