1. Introduction
The SoC FPGA Quad SPI Flash Controller is calibrated in the Preloader stage to determine the timing at which data can be most easily obtained.
As described above, QSPI access using the Preloader or U-Boot reflects the calibration results, so no user configuration is required. However, in the case of accessing QSPI in a later user application or in a RTOS in which the driver is implemented by the user, it is basically necessary to implement the same mechanism by the user or by using the calibration results of the Preloader.
This document explains how to determine the timing and how to check the results.
2. How QSPI Calibration in the Preloader Works
First, set the serial clock supplied to the QSPI device to a sufficiently slow clock and read the Device ID.
The value of the Device ID at this time is used as the value at the time of successful readout.
Then, switch to the target operating frequency and read the Device ID to the QSPI device while incrementing the Read Data Capture Delay register setting from 0.
If the read is successful, it is considered successful, and the value of the Read Data Capture Delay register at that time is adopted as the lower limit of the threshold value.
After that, the Read Data Capture Delay is incremented and the comparison is continued, and the Read Data Capture Delay value immediately before a mismatch with the value at the time of success is set as the upper limit of the threshold value.
Then, by taking a value halfway between the lower and upper limits, the value with the most margin is set.
Reference:
For more information on the Read Data Capture Delay register, please refer to the following document.
Cyclone® V HPS Memory Map
3. Introduction of the code that determines the Read Data Capture Delay value
As mentioned earlier, the Read Data Capture Delay determines the timing at which data can be captured most easily.
This chapter introduces the code that determines the value of Read Data Capture Delay as follows.
File path: uboot-socfpga\drivers\spi\cadence_qspi.c
[Figure 1] Code for setting Read Data Capture Delay
4. Read Data Capture Delay value to be checked on the log
The Preloader displays the Read Data Capture Delay value in the log.
The following is an excerpt from the actual log.
[Figure 2] Excerpt from the Prealoder log
In the above log, the lower and upper threshold limits and Read Data Capture Delay values are set as follows.
- Lower threshold limit: 0
- Upper Threshold Limit: 7
- Read Data Capture Delay value: 3
As you can see, the Read Data Capture Delay value can be checked from the log, so please check it if you have a chance.
Note
[Figure 2] is an image of Preloader v2013.01 (Cyclone® V / Arria® V) and v2014.10 (Arria® 10) or earlier. In case of the latest Preloader such as Quartus® Prime ver21.1_Std or ver21.3_Pro, the logs are different depending on the version, so if you do not see the logs, read the value of Rdelay (rddatacap) register to confirm.