* The original content was created in Japanese, so some information, images, and links may still be in Japanese. We’re updating gradually and appreciate your patience.
Introduction
One of the advantages of FPGAs traditionally considered is the ability to change pin assignments, pin attributes, and circuit functions after board creation and device implementation to address the risk of specification changes and design defects.
On the other hand, as memory and interfaces, including FPGAs, have become more powerful in recent years, many hard macros have been implemented in FPGAs, increasing the number of complex limitations that must be considered.
In addition, FPGAs are not necessarily upward compatible, so there are cases where existing design assets cannot be used without modification.
Therefore, it is essential to conduct a feasibility study prior to board design in order to mitigate serious risks such as board revision.
This document describes the items to be verified and how to check them.
The devices covered in this document are Intel® Arria® 10 FPGAs as examples, but can be used for any device family except for device-dependent portions.
Please use the latest version of Intel® Quartus® Prime to perform the feasibility study.
Contents
Examples of board revisions due to insufficient feasibility
Checklist
Feasibility Study
- Device Selection
- Skeleton Design
- Clock Resources, IP, Transceivers, I/O Interfaces, Hard Processor System (HPS)
- Compile the entire skeleton design
- Check power consumption
- Hardware verification (optional)
- Other notes
Download Documentation
Feasibility Study Design & Debugging Guidelines (Rev. 1) (Japanese)