1. Introduction
SoC FPGA can use the ECC function for the following devices.
[Source: Cyclone® V Hard Processor System Technical Reference Manual]
[Figure 1] Peripherals that can use the ECC function
Error injection can be used to verify that the ECC function actually works properly.
This article describes error injection.
2. Overview of Error Injection
Error injection is suitable when you want to check whether the ECC function works properly when reading data with ECC code.
Error Injection is a function in which System Manager intentionally embeds 1-bit or 2-bit errors in the data.
By using this function, you can check the behavior when reading data that is not normal.
3. Error Injection Setting Register
The error injection registers are different for SDRAM and other peripherals.
3-1. SDRAM
For SDRAM, the settings are made in the SDRAM Controller -> ctrlcfg register.
The setting Bit for Single-Bit and Double-Bit error injection is as follows.
- In case of Single-Bit -> Bit [13]: gensbe
- In case of Double-Bit -> Bit [14]: gendbe
Reference:
Please refer to the following document for details of the register.
Cyclone® V HPS Memory Map -> SDRAM Controller Address Map -> ctrlcfg
3-2. Other than SDRAM
For non-SDRAM, use the System Manager registers.
In the System Manager register, there is a register where ECC can be set for each peripheral other than SDRAM.
Reference:
For more information, please refer to the following document.
Cyclone® V Memory Map -> System Manager Module Address Map
For more information about the registers for each peripheral, please refer to the following document.
[Source: Cyclone® V HPS Memory Map]
[Figure 2] ECC setting registers for modules other than SDRAM
Using the L2 cache as an example, the settings for Single-Bit and Double-Bit are as follows.
- In case of Single Bit -> Bit [1]: injs
- In case of Double Bit -> Bit [2]: injd
Reference:
For more information, please refer to the following document.
Cyclone® V HPS Memory Map -> System Manager -> l2
For other peripherals, please check the setting points using the keywords "injs" for Single Bit and "injd" for Double Bit.
4. Usage of Error Injection
Error Injection is set using the registers introduced in "3. Error Injection Setting Register" above.
However, since the setting method differs between SDRAM and other peripherals, I will introduce the difference.
4-1. SDRAM
SDRAM can be used by writing with the error injection register set to High.
The image is as shown in Figure 3.
[Figure 3] Error Injection Settings (SDRAM)
4-2. Other than SDRAM
If other than SDRAM, it can be used by toggling the error injection register and writing within a certain time.
The image is as shown in Figure 4.
[Figure 4] Error Injection Settings (other than SDRAM)
5. Sample code introduction
Sample code for ECC for peripherals other than SDRAM is available from the manufacturer.
For SDRAM, it is sufficient to set gensbe / gendbe to High for error injection, whereas for other than SDRAM, injs / injd need to be toggled.
Therefore, the sample code for other than SDRAM peripherals is introduced here because it is useful.
Reference:
Sample code can be obtained from the following link.
SoC FPGA Bare-Metal Developer Center - 4. Examples
Additional bare-metal examples -> ECC
In the sample above, the configuration section for L2 cache error injection is introduced for your reference. (Figure ECC
[Figure 5] Error Injection Settings for L2 Cache
6. Summary
SoC FPGA can use ECC functionality for various peripherals, and error injection is used to verify that it works correctly.
The error injection settings are different for SDRAM and other peripherals.
For SDRAM, the error injection can be used by setting the error injection register to High and writing to SDRAM.
On the other hand, ohter than SDRAM peripherals can be used by toggling the error injection register and then writing to the SDRAM within a certain period of time.
When using ECC error injection in the future, please be careful with the setting method.