1. Introduction
This article describes the configuration register for mapping SDRAM to the Boot Region area of the address space (MPU view) as seen from the HPS (Arm processor) of an Intel® SoC FPGA.
We are often asked the question, "What memory is visible in this area after the boot is complete? We hope this article will help you to solve such questions.
The red frame in Figure 1 below corresponds to the Boot Region area. This article targets the Cyclone® V SoC, but the same concept applies to the Arria® V SoC and Arria® 10 SoC.
[Excerpt from the Cyclone® V Hard Processor System Technical Reference Manual]
[Figure 1] HPS Address Space
2. Change in SDRAM area during Boot ROM and after Preloader execution
As a conclusion, immediately after reset release (during Boot ROM program execution), the Boot Region area starts with Boot ROM mapped starting from 0, and after boot is completed (after Preloader execution), SDRAM is mapped.
Figure 2 below is a graphical summary of the SDRAM area.
[Figure 2] Change in SDRAM area
The memory to be shown in the Boot Region area is selected by the following two types of registers.
- l3regs.remap register (Address: 0xFF800000)
- MPUL2.Address Filtering register (Address: 0xFFFEFC00, 0xFFFEFC04)
The type of memory to be shown in the Boot Region area is selected from 0: ROM (Boot ROM) or 1: RAM (On-Chip RAM) by setting the bit0: mpuzero field in the l3regs.remap register, but SDRAM is not included in this register setting option. SDRAM is not present in this register setting. If SDRAM is to be shown in this area, the Address Filtering register setting in the L2 Cache Controller (MPUL2) must be changed.
Below are the details of the Address Filtering register and the actual settings to be made by the Preloader.
3. Address Filtering Register Specifications
The Address Filtering Register consists of the following two registers, which specify the Start Address and End Address of the area to show SDRAM.
- Address Filtering Start Register (Address: 0xFFFEFC00)
- Address Filtering End Register (Address: 0xFFFEFC04)
This chapter describes the settings for Start Address and End Address.
3-1. Address Filtering Start Register
The Address Filtering Start Register can be set with 0xFFFEFC00 and is as follows.
[Excerpt from the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual]
[Figure 3] Address Filtering Start Register Address
The contents of Figure 3 are as follows.
Bit [31:20] - This is where the SDRAM Start Address is set.
Since only 12 bits are reserved, set the upper 12 bits of the Start Address to
and the remaining lower 20 bits to 0x00000.
For example, if 0x001 is set, the Start Address of SDRAM is 0x00100000.
Bit [19:1] - Reserved
Bit [0] - Enables/disables address filtering.
To enable, set 0x1.
3-2. Address Filtering End Register
The Address Filtering End Register can be set to 0xFFFEFC04 and is as follows.
[Excerpt from the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual]
[Figure 4] Address Filtering End Register
The contents of Figure 4 are as follows.
Bit [31:20] - This is where the End Address of SDRAM is set.
As in the case of setting the Start Address, only the upper 12 bits of the End Address are set, The lower 20 bits are set to 0x00000.
Bit [19:0] - Reserved.
4. Preloader settings and results
The boot flow in the SoC FPGA is shown in Figure 5, and the Boot ROM → Preloader is executed in every flow.
[Excerpt from the HPS SoC Boot Guide - Cyclone® V SoC Development Kit]
[Figure 5] Boot Flow
In this section, we would like to check the Boot ROM point before Preloader execution and the Address Filtering setting after Preloader execution. (Confirmed with U-Boot SPL 2013.01.01).
4-1. Address Filtering during Boot ROM
The Address Filtering setting during boot ROM is as follows.
[Figure 6] Address Filtering during Boot ROM
・Contents of Address Filtering Start Register
The Start Address is set to 0x00100001.
Therefore, the settings are as follows.
Bit [31:20] - 0x001 ⇒ SDRAM Start Address is 0x00100000
Bit [0] - 0x1 ⇒ Address Filtering is Enable
・Address Filtering End Register setting
The End Address is 0xC0000000.
Therefore, the setting contents are as follows.
Bit [31:20] - 0xC00 ⇒ The End Address of SDRAM is 0xC0000000.
・The area of SDRAM during Boot ROM.
Since the Start Address is 0x00100000 and the End Address is 0xC0000000, the area of SDRAM during Boot ROM is 0x00100000 to 0xC0000000.
4-2. Address Filtering after Preloader execution
The Address Filtering setting after the Preloader is executed is as follows.
[Figure 7] Address Filtering after Preloader execution
・Contents of Address Filtering Start Register
The Start Address is set to 0x00000001.
Therefore, the settings are as follows.
Bit [31:20] - 0x000 ⇒ SDRAM Start Address is 0x00000000
Bit [0] - 0x1 ⇒ Address Filtering is Enable
・Address Filtering End Register setting
The End Address is set to 0xC0000000.
Therefore, the setting contents are as follows.
Bit [31:20] - 0xC00 ⇒ The End Address of SDRAM is 0xC0000000.
・The area of the SDRAM after the Preloader has been executed
Since the Start Address is 0x00000000 and the End Address is 0xC0000000, the area of SDRAM after the Preloader is executed is 0x00000000 to 0xC0000000.
5. Conclusion
As shown in "4-1 Address Filtering during Boot ROM" and "4-2 Address Filtering after Preloader execution", the type of memory visible in the Boot Region area differs between Boot ROM and after Preloader execution.
As you can see, the Boot Region (0x00000000 to 0x00100000) is allocated as part of the SDRAM area after the boot is completed (after the preloader is executed).