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FPGA-to-SDRAM interface opening configuration for SoC FPGAs (U-Boot 2019.04)

FPGA-to-SDRAM interface opening configuration for SoC FPGAs (U-Boot 2019.04)

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Introduction

The "bridge enable" command is used to open the bridge between the HPS-FPGA from U-Boot, but there are additional settings required in addition to "brdige enable" to use the F2S interface on Stratix® 10 SoC and Arria® 10 SoC.

__.png Reference: U-Boot HPS-FPGA Bridge Open Command for SoC FPGAs

This article describes the configuration required to open the FPGA-to-SDRAM (F2S) interface using the new version of U-Boot.

1. How to open the F2S interface by device family

The first operation required for all device families is to execute the "bridge enable" command. By executing this command, the registers required to use the bridge and interface between FPGA and HPS are set.

In addition to executing the command at the U-boot prompt (which can be entered by pressing the Enter key during the OS boot countdown), the command can also be executed by writing it in a U-boot script.

The following is a description of the operations and precautions required in addition to executing the "bridge enable" command for each device family, so please check the information for your device family.

1-1. Stratix® 10 SoC

For Stratix® 10 SoC, after executing "bridge enable", additional security firewall settings are required to allow access to the SDRAM controller.

The following document contains the commands to be executed and instructions on how to create a U-boot script file, please refer to the linked information.

__.png Reference: Creating the U-boot script

An example of register settings is shown below.

Configuration example:

To allow F2S0 to F2S2 to access all areas, use the following settings. Up to four accessible address regions can be defined for each F2Sx interface.

# Enable F2S0, F2S1 and F2S2 
mw 0xF8024050 0x00000092

# Initialize F2S0 (allow 4GB area from the top)
mw 0xF8020210 0x00000000    # region0addr_base Region0 top address (lower address)
mw 0xF8020214 0x00000000    # region0addr_baseext Top address of Region0
mw 0xF8020218 0xFFFFFFFF    # region0addr_limit End address of Region0
mw 0xF802021C 0x00000000    # region0addr_limitext end address of Region0 (lower address)
mw 0xF8020204 0x00000001    # enable_set region0enable=1 to enable Region0

# initialize F2S1 (allow 4GB area from top)
mw 0xF8020310 0x00000000    # region0addr_base Region0 start address (lower address)
mw 0xF8020314 0x00000000    # region0addr_baseext Region0 start address (upper address)
mw 0xF8020318 0xFFFFFFFF    # region0addr_limit Region0 end address (lower address)
mw 0xF802031C 0x00000000    # region0addr_limitext Region0 end address (lower address)
mw 0xF8020304 0x00000001    # enable_set region0enable=1 to enable Region0

# F2S2 initialization (allow 4GB area from the top)
mw 0xF8020410 0x00000000    # region0addr_base Region0 start address (lower address)
mw 0xF8020414 0x00000000    # region0addr_baseext Top address of Region0
mw 0xF8020418 0xFFFFFFFF    # region0addr_limit End address of Region0 (lower address)
mw 0xF802041C 0x00000000    # region0addr_limitext End address of Region0 (lower address)
mw 0xF8020404 0x00000001    # enable_set region0enable=1 to enable Region0

For details of registers to be set, refer to the register map.

__.png Reference: SDRAML3Interconnect Address Block Group

1-2. Arria® 10 SoC

The Arria® 10 SoC is similar to the Stratix® 10 SoC in that it requires a security firewall setting to allow access to the SDRAM controller in addition to "bridge enable".

However, in the case of the Arria® 10 SoC, it is possible to set the registers automatically when the boot loader is executed by setting the security firewall in the U-Boot device tree file in advance.

Also, since the device tree is generated with contents that allow access to the entire address space for F2S (4GB) as standard, no change is necessary in terms of opening the F2S interface. Please try this when you want to change the accessible range.

Description of the device tree:

The following is the device tree (devicetree.dts) for U-Boot generated by the bsp-create-settings tool. fpga2sdram0-0, fpga2sdram1-0, and fpga2sdram2-0 in the area enclosed by firewall {} are the relevant settings. The following is the relevant setting.

/* 
 * Driver: altera_arria10_soc_noc_arria10_uboot_driver 
 * Version: 1.0 
 * Binding: device 
 */ 
i_noc: noc@0xffd10000 { 
compatible = "altr,socfpga-a 10-noc"; 
reg = <0xffd10000 0x00008000>; 
reg-names = "mpu_m0"; 

firewall { 
/* 
 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base 
 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. .mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit 
 */ 
mpu0 = <0x00000000 0x0000ffff>;
/* 
 * Driver setting: altera_arria10_ soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base 
 * Driver setting: altera_arria10_soc_noc_arria10_ uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit 
 */ 
l3-0 = <0x00000000 0x0000ffff>;
/* 
 * Driver setting: altera_ arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base 
 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit 
 */ 
fpga2 sdram0-0 = <0x00000000 0x0000ffff>;
/* 
 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_ fpga2sdram_ddr_scr.fpga2sdram1region0addr.base 
 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_ mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit 
 */ 
fpga2sdram1-0 = <0x00000000 0x0000ffff>;
/* 
 * Driver setting: altera_arria10_ soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base 
 * Driver setting: altera_arria 10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit 
 */ 
fpga2sdram2-0 = <0x 00000000 0x0000ffff>;
}; 
}

Configuration change example:

For each of the three ports (fpga2sdram0 to 2) of the F2S interface, up to four accessible address regions (Regions) can be defined. regions are distinguished by a hyphenated number (-0 to 3) following fpga2sdramX.

An example of how to change the settings is shown below.

fpga2sdram0-0 = <0x00004000 0x00004fff>;
fpga2sdram1-0 = <0x00005000 0x00005fff>;
fpga2sdram1-1 = <0x00006800 0x00006fff>;
fpga2sdram2-0 = <0x00007000 0x00007fff>;
    • fpga2sdram port 1 (fpga2sdram0) ...  Accessible only from 0x40000000 to 0x4FFFFFFFFF
    • fpga2sdram port 2 (fpga2sdram1) ...  Accessible from 0x50000000 to 0x5FFFFFFFFF and from 0x68000000 to 0x6FFFFFFFFF (two regions defined)
    • fpga2sdram port 3 (fpga2sdram2) ...  Accessible only from 0x70000000 to 0x07FFFFFFF

The modified devicetree.dts file can then be used to implement the desired settings by following the U-Boot build procedure.

Please refer to the following article for the U-boot build procedure.

__.png Reference: Bootloader generation flow for SoC EDS v19.1 Std / v19.3 Pro and later (Arria® 10 SoC Edition)

Summary

These are the settings for opening the F2S interface.

Finally, we describe the advantage of the F2S interface: when accessing the HPS side from the FPGA side, accessing via the F2S interface allows direct access to the DDR memory connected to the SDRAM controller without passing through the main bus switch on the HPS side. This is advantageous for higher throughput access than via FPGA-to-HPS (F2H).

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