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IRQ port and interrupt pending register used for interrupts from FPGA to HPS

IRQ port and interrupt pending register used for interrupts from FPGA to HPS

  • Updated

1.　Introduction

Figure 1 below is part of a table that summarizes the port numbers (GIC Interrupt Number) that notify interrupts to the General Interrupt Controller (GIC) of the SoC FPGA and the interrupt factors.

There is also a port that signals an interrupt from the FPGA to the Arm® Cortex®-A9 processor in the HPS, so the Source Block has an entry called FPGA.

So how is the GIC Interrupt Number determined when notifying the Cortex®-A9 from the FPGA?

And where is the register to verify that the interrupt was properly notified?

This contents hope to help with such questions.

Figure 1. Excerpt from the GIC Interrupt Map

 

2.　GIC Interrupt Number when the interrupt is notified from the FPGA

The GIC Interrupt Number for interrupts from FPGA to Cortex-A9 can be determined in Platform Designer.

When interrupts from FPGA are enabled in the HPS settings, the ports named f2h_irq0 / f2h_irq1 are displayed.

Interrupt Number from FPGA to HPS is available from 72 to 135, and the assignment of f2h_irq0 / f2h_irq1 is as follows.

  • f2h_irq0: GIC Interrupt Number 72~103 
  • f2h_irq1: GIC Interrupt Number 104~135 

For details of Interrupt Number, please refer to "Table 10-3: GIC Interrupt Map" in the following document.

____.png Reference: Cyclone® V Hard Processor System Technical Reference Manual

When FPGA Module irq is connected to f2h_irq0 / f2h_irq1, numbers can be entered on the wires in the IRQ column of Platform Designer.

The number that can be entered on the wires is 0~31, and the number 0~31 on the wires corresponds to 72~103 for f2h_irq0 and 104~135 for f2h_irq1.

Figure 2 below shows an example of how the Interrupt Number is assigned.

InterruptNumberの割り当てられ方の例.png

Figure 2. Example of Interrupt Number Assignment

 

button_pio and jtag_uart are connected to h2f_irq0, and dipsw_pio is connected to h2f_irq1.

Since button_pio and jtag_uart are input on the wire as 1 and 2, respectively, the GIC Interrupt Number is 73 and 74, respectively.

Since dipsw_pio is input as 0 on the wire, the GIC Interrupt Number is 104.

 

3.　Interrupt Pending Register

In the previous section, we introduced the GIC Interrupt Number for interrupts from the FPGA. 
This section explains where the interrupt pending register in the Cortex®-A9 should be referenced.

Please refer to "3.2.6 Pending Set Registers (ICDISPRn)" in the following document for the interrupt pending registers.

____.png Reference: PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual

The bit number of the referenced interrupt pending register is tied to the 
GIC Interrupt Number as shown in Figure 3 below.

割り込みペンディング・レジスター.png

Figure 3. Interrupt Pending Register

 

The red frame indicates the pending register for notifying interrupts from the FPGA.

 

4.　Related information

The following two articles are useful for handling GICs.

__.png Reference: Cyclone®V SoC: HPS Register Specification List Sheet - (In Japanese)

For detailed specifications of the GIC, you need to check ARM's documentation. 
This article introduces URLs of documents related to GIC.

__.png Reference: Techniques for using Arm DS - Register View [2/3] Register Definitions by Yourself

We have published a register definition file to display the GIC registers in the DS-5 debugger. 
If you want to check the register values on the debugger GUI, please refer to this article.

 

5.　Conclusion

In this article, we introduced how to check the GIC Interrupt Number and interrupt pending registers in Platform Designer.

We hope you will find this article useful when you are setting interrupts from FPGA to Cortex®-A9.

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