1. Introduction
The Cyclone® V SoC / Arria® V SoC and Arria® 10 SoC are equipped with an Arm® Cortex®-A9 dual-core processor, which are referred to in this document as CPU0 and CPU1, respectively.
The SoC operates on CPU0 until U-boot in the boot flow, and if no operation is performed to boot CPU1, CPU1 will be in a reset state.
When using a multicore-compatible OS, CPU1 will be booted in the bootup code. However, if
OS is not used, or if the OS does not support multicore, the user will need to implement code to explicitly boot CPU1.
This article describes the procedure for users to explicitly activate dual-core.
Note:
Note that there are some differences in flow between the Cyclone® V SoC / Arria® V SoC and the Arria® 10 SoC. This article describes Cyclone® V SoC / Arria® V SoC.
2. CPU1 Startup Procedure
The startup procedure is shown in Figure 1 below.
First CPU0 starts up, and then CPU0 starts up CPU1. CPU0 needs to set the following registers to boot CPU1.
- remap register
- L2 Cache Address Filtering register
- cpu1startaddr register
- mpumodrst register (CPU1 reset release)
Figure 1. CPU1 startup procedure
3. Registers to be set
This chapter describes the registers (remap, L2 Cache Address Filtering, cpu1startaddr, and mpumodrst) set by CPU1.
3-1. remap register
The remap register is a register that specifies the memory to be mapped to address 0x0 and the settings to enable the HPS-FPGA bridge address space.
Depending on the setting of the first bit (bit 0) of the remap register, either BootROM or On Chip RAM can be selected for the area from 0x00000000 to 0x00100000 as seen from the MPU.
Since this register must be set so that BootROM is visible when CPU1 is booted, set the first bit of the reamp register in CPU0 as follows
- reamp [0] = 0x0
For details of the reamp register, please refer to the following document.
Reference material: Cyclone® V HPS Memory Map, remap
Figure 2. remap register address map
3-2. L2 Cache Address Filtering register
The L2 Cache Address Filtering register is a register in the L2 Cache category that sets where in the MPU address space SDRAM is presented.
The L2 Cache Address Filtering register consists of the following two registers to specify the Start Address and End Address of the area where SDRAM is shown.
- L2 Cache Address Filtering Start Register (Address: 0xFFFEFC00)
- L2 Cache Address Filtering End Register (Address: 0xFFFEFC04)
When CPU1 starts up, the BootROM must be visible in the area from 0x00000000 to 0x00100000.
Therefore, this area should be set as shown below so that SDRAM is not visible.
- Address Filtering Start Register (Address: 0xFFFEFC00) = 0x00100001
Please refer to the following document for the specifications of the L2 Cache Address Filtering register.
Reference material: State of SDRAM area address mapping setting before and after SoC FPGA boot - (In Japanese)
See the chapter "3. Address Filtering Register Specifications".
3-3. cpu1startaddr register
The cpu1startaddr register registers the entry point (start address) to which CPU1 jumps.
This 32-bit register is used to set the entry point address.
For details of the cpu1startaddr register, please refer to the following document.
Reference material: Cyclone® V HPS Memory Map, cpu1startaddr
Figure 3. cpu1startaddr Register Address Map
3-4. mpumodrst register
The mpumodrst register is a register that controls the reset of the CPU, etc.
CPU1 is de-reset by this mpumodrst register.
The second bit (bit 1) of the mpumodrst register is the reset release of CPU1, so set as follows.
- mpumodrst [1] = 0x0
For details on the mpumodrst register, please refer to the following document.
Reference material: Cyclone® V HPS Memory Map, mpumodrst
Figure 4. mpumodrst Register Address Map
4. Sample Code
The following is sample code for setting the registers introduced in the previous chapter.
This content is an example code to be implemented in CPU0 to boot CPU1.
Figure 5. Sample Code for Register Setting
5. Precautions
Before resetting CPU1, it is necessary to store the CPU1 execution binary to memory in advance.
The method of storing the binary is up to you, but as an example this time, we will introduce the flow of expanding the CPU0 / CPU1 execution binary stored in the FAT area of the SD card to SDRAM and then executing it.
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1. store CPU0 and CPU1 execution binaries in the FAT area of the SD card
2. Execute U-boot and prepare command line.
3. Use the following command to extract the CPU0 and CPU1 binaries to SDRAM.
fatload mmc 0 0x00900000 cpu1_main.bin
fatload mmc 0 0x00200000 cpu0_main.bin
4. Execute the code for CPU0 with the following command.
go 0x00200000
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Point:
The command argument addresses (placement of binaries for CPU0 and CPU1) are just an example.
Here, the entry point for the application for CPU0 is 0x00200000.
cpu1startaddr register is 0x00900000, and the entry point for CPU1 is 0x00900000.
is used as the assumption for the configuration. Example 6.
6. Conclusion
In this article, we introduced how to start up the second core.
When actually starting the second core, the remap register, L2 Cache Address Filtering register, cpu1startaddr register, and mpumodrst register must be set in the CPU0 program code.
I hope you will refer to this article.