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How to set priority in memory access for SoC FPGAs (Cyclone® V SoC/ Arria® V SoC)

How to set priority in memory access for SoC FPGAs (Cyclone® V SoC/ Arria® V SoC)

  • Updated

1 .　Introduction.

The SDRAM Controller inside the SoC FPGA HPS contains a Multi-Port Front End (MPFE) that mediates access to SDRAM from each port.

The MPFE arbitration is configured by dedicated registers for priority and weight, respectively.

This article provides an overview of MPFE and its arbitration settings.

This article is written for the Cyclone® V SoC / Arria® V SoC. 2.

 

Overview of MPFE

MPFE is a mediation circuit included in the SDRAM Controller.

It is responsible for regulating simultaneous accesses to the SDRAM Controller from the FPGA, MPU, and L3 Interconnect.

Please refer to the following reference document for a block diagram of the connection between the MPFE and FPGA/MPU/L3 Interconnect.

____.png See 
Cyclone® V Hard Processor System Technical Reference Manual 
Figure 12-1: SDRAM Controller Subsystem High-Level Block Diagram

 

Specific details of the arbitration are as follows, Prioritization and the weight of each port for round-robin accesses when the priorities are the same. weighting of each port for round-robin access in the case of equal priority. for round-robin accesses with the same priority.

For example, if the priority is set higher for the FPGA than for the MPU, the MPU will wait until the FPGA transfer is complete.

If two accesses with the same priority occur at the same time, they will be round-robin accesses, but the ratio of the accesses can be set by setting the weights.

There are a total of 10 ports for MPFE, and the details are shown in the figure below.

 

  • Command Port 0, 2, 4: FPGA fabric AXI read command ports / FPGA fabric Avalon-MM read or write command ports 

  • Command Port 1, 3, 5: FPGA fabric AXI write command ports / FPGA fabric Avalon-MM read or write command ports

  • Command Port 6: L3 AXI read command port

  • Command Port 7: MPU AXI read command port

  • Command Port 8: L3 AXI write command port

  • Command Port 9: MPU AXI write command port

For details, please refer to the following reference documents.

____.png Reference material: 
Cyclone® V Hard Processor System Technical Reference Manual
　　Refer to Table 12-4: HPS SDRAM MPFE Command Port Mapping. 3.

 

 

MPFE Configuration Register

As briefly mentioned in "2. MPFE Overview," the MPFE can be used to set prioritization and weight settings. This chapter describes the details of each setting. 

 

3-1. prioritization setting

Prioritization is set by the mppriority register shown below (see Figure 1).

  • mppriority (0xFFC250AC)

For details on the mppriority register, please refer to the following document.

____.png Reference: 
Cyclone® V HPS Memory Map - mppriority


In the mppriority register, 3 bits are allocated for each port to set the priority value, and since there are 10 ports in total, the number of valid bits is 30.

The breakdown of the mppriority register is shown in the figure below.

 

Figure 1: Breakdown of the mppriority register


The mppriority registers for each port are as follows.

  • Priority value 0x0 to 0x7 (the higher the number, the higher the priority)

The following figure shows an example of the mppriority setting.

 

Figure 2: Example of mppriority register setting

 

 

3-2. weight setting

The weight is set by the following four registers.

  • mpweight_0_4 (0xFFC250B0)
  • mpweight_1_4 (0xFFC250B4)
  • mpweight_2_4 (0xFFC250B8)
  • mpweight_3_4 (0xFFC250BC)

For details of each register, please refer to the following document.

____.png Reference materials: 
Cyclone® V HPS MemoryMap- mpweight_0_4
Cyclone® V HPS Memory Map - mpweight_1_4
Cyclone®V HPS Memory Map - mpweight_2_4
mpweight_3_4
 


The weights must be set to the sum of the weights for each port and the weights for each priority level.

The weight of each port is called the Static Weight, and the sum of the weights of each priority is called the Sum of Weight. 

 

3-2-1. Setting Static Weight (weight of each port)

In [31:0] mpweight_0_4 / [17:0] mpweight_1_4, each port is allocated 5 bits to set the weight, and since there are 10 ports in total, the number of valid bits is 50.

The set value of the weight for each port is as follows.

  • Weight setting value 0x0 to 0x1F

The following figure shows the breakdown of the Static Weight setting registers.

 

Figure 3 Static Weight Setting Register 

 

3-2-2 Sum of Weight (sum of weights for each priority)

In [31:18] mpweight_1_4 / [31:0] mpweight_2_4 / [17:0] mpweight_3_4, 8 bits are allocated for each priority level to set the sum of weights, and since there are 8 priorities from 0x0 to 0x7, the effective bits are 64 bits. Breakdown of Sum of Weight setting register

The following figure shows the breakdown of the Sum of Weight setting register.

 

Figure 4 Sum of Weight Setting Register

 

Cautions

The SDRAM Controller updates the priority and weight every 10 cycles of the Controller's internal clock. 
Therefore, please note that the priority and weight may not be updated immediately after setting.

____.png Reference: 
Cyclone® V Hard Processor System Technical Reference Manual 
　　See MPFE Multi-Port Arbitration Considerations for Use

<Excerpt 
The memory controller commits the priority and weight registers into the MPFE The memory controller commits the priority and weight registers into the MPFE arbiter once every 10 SDRAM clock cycles. 5. 

 

Conclusion

This article has provided an overview of MPFE and its configuration.

If you want to set up MPFE arbitration, you need to set up each register.

To set the priority, you need to set mppriority, and to set the weight, you need to set mpweight_0_4 / mpweight_1_4 / mpweight_2_4 / mpweight_3_4.

We hope this will be helpful when actually checking and changing the priority and weight settings.

 

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