Introduction.
This article describes the device/board-dependent settings and definitions included in the boot loader (U-Boot) for Altera® SoC FPGA devices. In past versions, each device family used a different version of the U-Boot, but starting with SoC FPGA Embedded Development Suite (SoC EDS) version 19.1 and later, the U-Boot source tree is common to all families.
In addition, recent U-Boot versions have also introduced the concept of devicetrees traditionally used in Linux, so some device/board-dependent settings are now described as parameters in the devicetree instead of definitions in the source code.
Below is a description of the device/board-dependent files for each SoC FPGA device family.
Please refer to the following link for the source code and build procedure of the boot loader (U-Boot).
Reference: Altera Opensource - github.com " u-boot-socfpga - socfpga_v2020.04 ".
Reference: Rocketboards.org " Building Bootloader (Building the latest bootloader for SoC FPGA devices) ".
1. Device/Board Dependent File Types
The device/board-dependent implementation is mainly divided into the following four types.
In addition to handoff information, there are other device/board-dependent implementations. In particular, when an original board is created, it is necessary to determine whether or not each file needs to be edited.
Table 1. Types of Device/Board Dependent Files
| Type | Summary | Implementation Location |
| Handoff | Information inherited from options set on the Quartus® Prime project (implementation varies by device family) |
Varies by device family |
| defconfig | File containing configuration information for the U-Boot Definitions applied by make xxx_defconfig at the beginning of the build |
Under configs |
| include/configs | Header file containing board-specific definitions include/configs/<CONFIG_SYS_CONFIG_NAME>.h |
under include/configs |
| Devicetree | Contains configuration parameters for devices/peripherals. Extension: dts, dtsi (main is dts file, dtsi is for include only) |
arch/arm/dts and below |
Each file is described below.
2. Handoff
This information is used to take over the Pin and HPS configuration parameters that are set in the Quartus® Prime project. The method of reflecting handoff information in the bootloader source tree differs for each device family.
Point:
Please note that if you change the settings in the Quartus® Prime project, the new handoff information must be reflected in the bootloader.
The main changes that affect handoff include HPS-related pin settings, SDRAM controller settings for the HPS, and HPS option changes (it is recommended that the handoff information be reapplied when the FPGA-side design is complete).
2-1. Handoff for Cyclone® V SoC / Arria® V SoC
Following the bootloader build procedure, run bsp-create-settings, qts-filter.sh, and the following files will be reflected in the source tree (board/altera/cyclone5-socdk/qts).
- iocsr_config.h ... Configuration of HPS-side I/O (I/O configuration by Scan Manager)
- pinmux_config.h ... Function selection for HPS-side I/O (pin multiplexer configuration)
- pll_config.h ... Clock setting for HPS internal PLL
- sdram_config.h ... SDRAM controller settings
2-2. Handoff for Arria® 10 SoC
Following the build procedure, bsp-create-settings will generate the handoff information in devicetree format (devicetree.dts). The handoff information is reflected by removing unnecessary descriptions (dts-v1, chosen) from this file and copying it over to arch/arm/dts/socfpga_arria10-handoff.dtsi.
See devicetree.dts for details (including PLL, PinMux, I/O Config, HPS-FPGA Bridge settings, etc.).
If you want to remove unnecessary information from devicetree.dts, you can use the following command.
sed -i '/dts-v1/d' devicetree.dts
sed -i '/chosen/,+4d' devicetree.dts
2-3. Handoff for Stratix® 10 SoC / Agilex™ SoC
For these families, the handoff equivalent information is contained in the configuration data (.sof). No input of handoff information is required during bootloader generation.
Both the 1st Stage boot loader (FSBL) and handoff information are loaded into RAM by the Secure Device Manager (SDM) during boot execution, and the handoff information is referenced from the FSBL.
The handoff contents can be checked by opening the text files under the output_files directory (asm_hps_handoff_data_dump.txt and hps_handoff_array_formated. txt) under the output_files directory (PLL, PinMux, I/O Config, Misc, etc.).
3. defconfig
File for configuration of the U-Boot environment. This file contains various option settings starting with CONFIG_xxx as follows
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_ENV_ OFFSET=0x200000
CONFIG_DM_GPIO=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA10_ SOCDK=y
CONFIG_ENV_OFFSET_REDUND=0x210000
:Since a file for the Development Kit is provided for each device family, the following files can be used without modification when verifying with the Development Kit.
- socfpga_cyclone5_defconfig
- socfpga_arria5_defconfig
- socfpga_arria10_defconfig
- socfpga_stratix10_defconfig
- socfpga_agilex_defconfig
In addition to the above, various defconfig for 3rd party evaluation boards, QSPI boot and NAND boot of the original Development Kit, etc. are included in the source tree. It is easy to support the original board by editing necessary parts based on the defconfig that is prepared in advance.
Point:
Option item includes items to select the vendor and series of QSPI Flash device and Ethernet PHY device, so if you use a different device from the Development Kit, you need to change these options.
- CONFIG_SPI_FLASH_STMICRO=y ... QSPI Flash ("STMICRO" can be changed to "MACRONIX" etc.)
- CONFIG_PHY_MICREL=y ... Ethernet PHY vendor
- CONFIG_PHY_MICREL_KSZ90X1=y ... Ethernet PHY Series
All options for vendors that are not used basically to reduce code size are disabled. The available options can be found in Kconfig and menuconfig in the source tree.
Figure 1. Example of menuconfig display
4. include/configs
According to the target board selection option (CONFIG_TARGET_xxx) included in defconfig, <CONFIG_SYS_CONFIG_NAME>.h under the include/configs directory is included during build execution. <CONFIG_SYS_CONFIG_NAME>.h is included at build time. <CONFIG_SYS_CONFIG_NAME>.h and the header files included from it also contain device/board dependent definitions.
The header file used (CONFIG_SYS_CONFIG_NAME) is specified in arch/arm/mach-socfpga/Kconfig as follows
config SYS_CONFIG_NAME
default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA 5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDKThe setting status of CONFIG_SYS_CONFIG_NAME can be checked by opening u-boot.cfg in the source tree Top directory or by searching for SYS_CONFIG_NAME on menuconfig (by typing '/' key).
Point:
If the DDR memory size on the original board is smaller than that of the Development Kit, be careful with the setting value of PHYS_SDRAM_1_SIZE. If the memory size is other than 1GB, PHYS_SDRAM_1_SIZE must be changed.
Excerpt from socfpga_cyclone5_socdk.h:
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */Excerpt from socfpga_soc64_common.h ( include from socfpga_stratix10_socdk.h etc):
/*
* External memory configurations
*/
#define PHYS_SDRAM_1 0x0
#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
5. Devicetree
The devicetree file (.dtb) is generated from the devicetree source (.dts) stored under arch/arm/dts. The source describes parameter settings for various peripherals, but the syntax and configuration items are generally the same as those in the devicetree applied to Linux device drivers.
Some U-Boot specific properties such as "u-boot,dm-pre-reloc" and "u-boot,dm-spl" are included. The devicetree can be applied to SPL as well as U-Boot, but the devicetree applied to SPL is extracted from the devicetree for U-Boot to reduce the file size, and only the definitions containing the "u-boot,dm-pre-reloc" or "u-boot,dm-spl" property from the devicetree for U-Boot (this specification is described in the text document "doc/driver-model/design.rst" included in the U-Boot source tree).
Point:
If the Arria® 10 SoC is the target, handoff information is also included in the devicetree (.dtb) (as applied by socfpga_arria10-handoff.dtsi described above).
The devicetree to be used is selected by CONFIG_DEFAULT_DEVICE_TREE specified in defconfig. The CONFIG_DEFAULT_DEVICE_TREE setting can be checked by opening u-boot.cfg in the Top directory of the source tree, or by searching for DEFAULT_DEVICE_TREE on menuconfig (by typing '/').
Point:
The devicetree also contains DDR memory size definitions, so if you are changing from the size in the Development Kit (1GB), you will need to change the memory definitions in the devicetree source as well.
The following is the definition of memory included in the devicetree source. The base address (0x0) and size (1GB: 0x40000000) are specified in "reg = <0x0 0x40000000>;".
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
u-boot,dm-pre-reloc;
};
Other definitions for devices/peripherals should also be changed as needed.
Conclusion
In this article, we introduced the device/board-dependent definitions included in U-Boot.
Some of the points described in the " Point" section are based on common problems that occur when starting up a board when an original board is created.
Please refer to them when generating a boot loader for your original board.