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How to set CL/CWL (CAS Latency, CAS Write Latency) for EMIF IP

How to set CL/CWL (CAS Latency, CAS Write Latency) for EMIF IP

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Introduction

The EMIF (External Memory Interface) IP provides latency (CL: CAS latency, CWL: CAS Write latency) settings.

The latency setting must be read from the speed bin that represents the speed grade of the DDR memory (SDRAM) and must be set correctly.

The memory datasheet lists the timing values, including latency, for each speed bin. If those values are not set correctly in the EMIF IP, unexpected malfunctions such as bit corruption of data may occur.
This article will focus on latency settings, how to read latency from speed bins, where to set the EMIF IP, and some notes and FAQs.

 

How to Read from a DDR Memory Datasheet

First, we will show you how to properly read the latency. The procedure is as follows

  1. Obtain the datasheet for the DDRx SDRAM you are using
  2. Select the "Speed Bin" table that lists the appropriate speed grade
    Figure: How to confirm Speed Bin (Ex. Using 333.33MHz with DDR3-1333G)

  3. Select the column for the appropriate speed grade (and device revision) (①)
    • Example: DDR3-1333G
  4. Find the clock period tCK(avg) based on the memory clock frequency to be used, and look for a location in the min-max range in the table (multiple locations may be applicable) (②)
    • Example: For 333.333MHz, tCK(avg) = 3.0 (ns), so (min, max) = (2.5, 3.3) applies to two locations.
    • Cannot be used if "Reserved".
    • If a condition is noted as "Option(al)", it can be used if the condition is met.
  5. In the table, the condition shown in the "Parameter" column to the left of the row is a possible setting (③)
    • Read the values of CL and CWL (e.g., CL=5, CWL=5 or CL=6, CWL=5)
    • (In the case of DDR2, CWL is not defined separately, so it is sufficient to read only the CL value.

(Notes.)

  • If the max value of the clock period (tCK) uses an inequality sign "<" (no equal sign), then the value exactly at that value should be considered not applicable.
    • In the above example, the memory clock is 400 MHz, tCK=2.5(ns), but the 333. . MHz, tCK=3.0(ns), the same condition (CL=5, CWL=5 or CL=6, CWL=5) as in the example
      (CL=7, CWL=6 does not include < 2.5 and tCK=2.5, so it is not applicable)
  • In the case of DDR4, the possible CAS Latency values vary depending on whether Read DBI is off or on, so read it as a condition


Ex. Speed Bin description in SDRAM datasheet(DDR4-2133)

 

EMIF IP setting point

Set the obtained CL and CWL to the EMIF IP. The settings can be changed on the following screens.

In case of IP Toolbench GUI

    • Memory Parameters tab -> Memory Initialization Options category
    • Setting location: [CL] Memory CAS latency setting
      [CWL] Memory write CAS latency setting mceclip5.png

For Platform Designer GUI

    • Memory tab -> Latency and Burst category
    • Setting location: [CL] Memory CAS latency setting
      [CWL] Memory write CAS latency setting mceclip6.png

 

FAQ (Frequently Asked Questions)

Q. The memory clock frequency has been changed due to a specification change. Is there anything I should be aware of?

A. If the memory clock frequency is changed, the CAS latency and CAS write latency values may no longer be appropriate. Be sure to set the settings according to the memory clock frequency.

 

Q. Some boards that use the Intel® Arria®10 FPGA DDR4 EMIF IP rarely have data errors. Is there a problem with the following settings?
Memory operating frequency 1066.667MHz, Read DBI OFF, Cas Latency [CL] = 18, Cas Write Latency [CWL] = 16

A. The operating frequency (period tCK), Read DBI on/off, CL, and CWL values should be set to the correct values listed in the Speed Bin of the memory's data sheet.
(The above settings are not a supported combination according to your SDRAM datasheet.)

 

Q. I initially designed with a frequency of 1200 MHz, but when the frequency was lowered for a change, I thought the change was unnecessary for the following reason. Is this an error?
(a) Since the clock frequency is lowered, the timing is in the direction of being relaxed, especially other values do not need to be changed
(b) Since CL and CWL are increased from the values corresponding to 1066.667MHz (ex. CL=16, CWL=14), there is no problem
(c) In DDR4 standard document (JESD-79A Nov./2013) 1066.667 MHz is the same as 1200 MHz under the condition tCK < 0.938

A. False. Check the Speed Bin table in the memory vendor's datasheet for the setting.
Any combination not listed in the table is not appropriate even if the Setup time condition is relaxed in terms of timing.
Please check the vendor's datasheet as tCK < 0.937 in some cases.

 

Conclusion

In this article, we have explained how to read latency from speed bins and where to set the EMIF IP. It also includes notes and frequently asked questions. Set the correct CAS Latency and CAS Write Latency to ensure that your design works reliably.

 

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