Description.
As memory interfaces increase in speed, the data validation window is shrinking and signal quality is deteriorating.
Since the time spent on verification and debugging to meet specification requirements is on the rise, it is important to design devices and boards according to the appropriate procedures and to implement means for debugging in advance during the design phase.
This document shows the "design flow" and "debug flow" and aims to prevent defects from being mixed in by following the appropriate design procedures and to solve problems quickly by implementing the necessary debugging mechanisms. The objective is to prevent defects by following the proper design procedures and to solve problems quickly by implementing the necessary mechanisms for debugging.
- Target devices: Stratix® V FPGAs, Arria® V FPGAs, Cyclone® V FPGAs
- Target memory standards: DDR2, DDR3(L)
Contents
- Introduction
- Design Flow
- Debug Flow
- Appendix
- Checklist
- How to Check Parameters
- How to create an Example Design
- Checklist for using the EMIF Toolkit
Design and Debug Guidelines (Rev. 1.1) / For V Series: Stratix® V, Arria® V, Cyclone® V