Introduction
In a system that outputs data and inverted clock from an FPGA to a device that requires a Source Synchronous center-aligned input, what would the SDC settings and analysis results look like?
This article presents SDC and analysis results using a simple system as an example.
System Configuration and Interface Specifications
Let's consider an example when the system configuration and Interface specifications are as shown in the figure below.
SDC Constraints
Set the clock with create_generated_clock to CLK_OUT which will be used as the latch clock on the receiving device.
Board delay is not taken into account.
derive_pll_clocks -create_base_clocks
create_generated_clock -name CLK_OUT -source [get_pins {<The clock that synchronizes the DDIOs>}] [get_ports {CLK_OUT}]
The Value of set_output_delay sets the specification required when CLK_OUT latches as shown in Figure 2.
set_output_delay -clock {CLK_OUT} -max 4.000 [get_ports {DATA_OUT}]
set_output_delay -clock {CLK_OUT} -min -4.000 [get_ports {DATA_OUT}]
Note that the concept changes depending on the notation and type of the receiving device specifications.
Report Timing
Create a Netlist for timing analysis in Timing Analyzer.
Open the Report Timing Setup screen, set Report conditions, etc., and click Report Timing.
In Setup analysis of Report Timing, you can analyze the result set by -max of set_output_delay.
In Hold analysis of Report Timing, you can analyze the result set by -min of set_output_delay.
This completes the SDC example and analysis for Source Synchronous Output.
Please take a look at them for reference.