# Reading pref.tcl
# do presspb_led_nios2_run_msim_rtl_verilog.do
# if ![file isdirectory presspb_led_nios2_iputf_libs] {
# 	file mkdir presspb_led_nios2_iputf_libs
# }
# 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying D:/intelFPGA/20.1/modelsim_ae/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
###### Libraries for IPUTF cores 
# vlib presspb_led_nios2_iputf_libs/error_adapter_0
# vmap error_adapter_0 ./presspb_led_nios2_iputf_libs/error_adapter_0
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap error_adapter_0 ./presspb_led_nios2_iputf_libs/error_adapter_0 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/avalon_st_adapter
# vmap avalon_st_adapter ./presspb_led_nios2_iputf_libs/avalon_st_adapter
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap avalon_st_adapter ./presspb_led_nios2_iputf_libs/avalon_st_adapter 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/rsp_mux_001
# vmap rsp_mux_001 ./presspb_led_nios2_iputf_libs/rsp_mux_001
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap rsp_mux_001 ./presspb_led_nios2_iputf_libs/rsp_mux_001 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/rsp_mux
# vmap rsp_mux ./presspb_led_nios2_iputf_libs/rsp_mux
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap rsp_mux ./presspb_led_nios2_iputf_libs/rsp_mux 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/rsp_demux
# vmap rsp_demux ./presspb_led_nios2_iputf_libs/rsp_demux
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap rsp_demux ./presspb_led_nios2_iputf_libs/rsp_demux 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/cmd_mux_001
# vmap cmd_mux_001 ./presspb_led_nios2_iputf_libs/cmd_mux_001
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap cmd_mux_001 ./presspb_led_nios2_iputf_libs/cmd_mux_001 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/cmd_mux
# vmap cmd_mux ./presspb_led_nios2_iputf_libs/cmd_mux
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap cmd_mux ./presspb_led_nios2_iputf_libs/cmd_mux 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/cmd_demux_001
# vmap cmd_demux_001 ./presspb_led_nios2_iputf_libs/cmd_demux_001
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap cmd_demux_001 ./presspb_led_nios2_iputf_libs/cmd_demux_001 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/cmd_demux
# vmap cmd_demux ./presspb_led_nios2_iputf_libs/cmd_demux
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap cmd_demux ./presspb_led_nios2_iputf_libs/cmd_demux 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/router_003
# vmap router_003 ./presspb_led_nios2_iputf_libs/router_003
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap router_003 ./presspb_led_nios2_iputf_libs/router_003 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/router_002
# vmap router_002 ./presspb_led_nios2_iputf_libs/router_002
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap router_002 ./presspb_led_nios2_iputf_libs/router_002 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/router_001
# vmap router_001 ./presspb_led_nios2_iputf_libs/router_001
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap router_001 ./presspb_led_nios2_iputf_libs/router_001 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/router
# vmap router ./presspb_led_nios2_iputf_libs/router
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap router ./presspb_led_nios2_iputf_libs/router 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_agent_rsp_fifo
# vmap jtag_uart_avalon_jtag_slave_agent_rsp_fifo ./presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_agent_rsp_fifo
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap jtag_uart_avalon_jtag_slave_agent_rsp_fifo ./presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_agent_rsp_fifo 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_agent
# vmap jtag_uart_avalon_jtag_slave_agent ./presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_agent
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap jtag_uart_avalon_jtag_slave_agent ./presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_agent 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/nios2_cpu_data_master_agent
# vmap nios2_cpu_data_master_agent ./presspb_led_nios2_iputf_libs/nios2_cpu_data_master_agent
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap nios2_cpu_data_master_agent ./presspb_led_nios2_iputf_libs/nios2_cpu_data_master_agent 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_translator
# vmap jtag_uart_avalon_jtag_slave_translator ./presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_translator
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap jtag_uart_avalon_jtag_slave_translator ./presspb_led_nios2_iputf_libs/jtag_uart_avalon_jtag_slave_translator 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/nios2_cpu_data_master_translator
# vmap nios2_cpu_data_master_translator ./presspb_led_nios2_iputf_libs/nios2_cpu_data_master_translator
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap nios2_cpu_data_master_translator ./presspb_led_nios2_iputf_libs/nios2_cpu_data_master_translator 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/cpu
# vmap cpu ./presspb_led_nios2_iputf_libs/cpu
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap cpu ./presspb_led_nios2_iputf_libs/cpu 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/rst_controller
# vmap rst_controller ./presspb_led_nios2_iputf_libs/rst_controller
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap rst_controller ./presspb_led_nios2_iputf_libs/rst_controller 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/irq_mapper
# vmap irq_mapper ./presspb_led_nios2_iputf_libs/irq_mapper
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap irq_mapper ./presspb_led_nios2_iputf_libs/irq_mapper 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/mm_interconnect_0
# vmap mm_interconnect_0 ./presspb_led_nios2_iputf_libs/mm_interconnect_0
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap mm_interconnect_0 ./presspb_led_nios2_iputf_libs/mm_interconnect_0 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/pb_pio
# vmap pb_pio ./presspb_led_nios2_iputf_libs/pb_pio
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap pb_pio ./presspb_led_nios2_iputf_libs/pb_pio 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/onchip_memory
# vmap onchip_memory ./presspb_led_nios2_iputf_libs/onchip_memory
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap onchip_memory ./presspb_led_nios2_iputf_libs/onchip_memory 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/nios2_cpu
# vmap nios2_cpu ./presspb_led_nios2_iputf_libs/nios2_cpu
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap nios2_cpu ./presspb_led_nios2_iputf_libs/nios2_cpu 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/led_pio
# vmap led_pio ./presspb_led_nios2_iputf_libs/led_pio
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap led_pio ./presspb_led_nios2_iputf_libs/led_pio 
# Modifying modelsim.ini
# vlib presspb_led_nios2_iputf_libs/jtag_uart
# vmap jtag_uart ./presspb_led_nios2_iputf_libs/jtag_uart
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap jtag_uart ./presspb_led_nios2_iputf_libs/jtag_uart 
# Modifying modelsim.ini
###### End libraries for IPUTF cores 
###### MIF file copy and HDL compilation commands for IPUTF cores 
# 
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_ociram_default_contents.dat ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_ociram_default_contents.hex ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_ociram_default_contents.mif ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_rf_ram_a.dat ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_rf_ram_a.hex ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_rf_ram_a.mif ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_rf_ram_b.dat ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_rf_ram_b.hex ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_rf_ram_b.mif ./
# file copy -force C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_onchip_memory.hex ./
# 
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -work error_adapter_0                           
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:52 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv -work error_adapter_0 
# -- Compiling module nios2_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0
# End time: 15:09:52 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter.vhd"                -work avalon_st_adapter                         
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:54 on Jan 26,2021
# vcom -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter.vhd -work avalon_st_adapter 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity nios2_system_mm_interconnect_0_avalon_st_adapter
# -- Compiling architecture rtl of nios2_system_mm_interconnect_0_avalon_st_adapter
# End time: 15:09:54 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_rsp_mux_001.sv"                       -work rsp_mux_001                               
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:54 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_rsp_mux_001.sv -work rsp_mux_001 
# -- Compiling module nios2_system_mm_interconnect_0_rsp_mux_001
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_rsp_mux_001
# End time: 15:09:54 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv"                                         -work rsp_mux_001                               
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:54 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv -work rsp_mux_001 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 15:09:54 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_rsp_mux.sv"                           -work rsp_mux                                   
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:54 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_rsp_mux.sv -work rsp_mux 
# -- Compiling module nios2_system_mm_interconnect_0_rsp_mux
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_rsp_mux
# End time: 15:09:54 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv"                                         -work rsp_mux                                   
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:54 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv -work rsp_mux 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 15:09:55 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_rsp_demux.sv"                         -work rsp_demux                                 
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:55 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_rsp_demux.sv -work rsp_demux 
# -- Compiling module nios2_system_mm_interconnect_0_rsp_demux
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_rsp_demux
# End time: 15:09:55 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_mux_001.sv"                       -work cmd_mux_001                               
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:55 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_mux_001.sv -work cmd_mux_001 
# -- Compiling module nios2_system_mm_interconnect_0_cmd_mux_001
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_cmd_mux_001
# End time: 15:09:55 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv"                                         -work cmd_mux_001                               
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:55 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv -work cmd_mux_001 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 15:09:55 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_mux.sv"                           -work cmd_mux                                   
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:55 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_mux.sv -work cmd_mux 
# -- Compiling module nios2_system_mm_interconnect_0_cmd_mux
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_cmd_mux
# End time: 15:09:55 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv"                                         -work cmd_mux                                   
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:55 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_arbitrator.sv -work cmd_mux 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 15:09:56 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_demux_001.sv"                     -work cmd_demux_001                             
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:56 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_demux_001.sv -work cmd_demux_001 
# -- Compiling module nios2_system_mm_interconnect_0_cmd_demux_001
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_cmd_demux_001
# End time: 15:09:56 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_demux.sv"                         -work cmd_demux                                 
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:56 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_cmd_demux.sv -work cmd_demux 
# -- Compiling module nios2_system_mm_interconnect_0_cmd_demux
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_cmd_demux
# End time: 15:09:56 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router_003.sv"                        -work router_003                                
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:56 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router_003.sv -work router_003 
# -- Compiling module nios2_system_mm_interconnect_0_router_003_default_decode
# -- Compiling module nios2_system_mm_interconnect_0_router_003
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_router_003
# End time: 15:09:56 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router_002.sv"                        -work router_002                                
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:56 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router_002.sv -work router_002 
# -- Compiling module nios2_system_mm_interconnect_0_router_002_default_decode
# -- Compiling module nios2_system_mm_interconnect_0_router_002
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_router_002
# End time: 15:09:57 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router_001.sv"                        -work router_001                                
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:57 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router_001.sv -work router_001 
# -- Compiling module nios2_system_mm_interconnect_0_router_001_default_decode
# -- Compiling module nios2_system_mm_interconnect_0_router_001
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_router_001
# End time: 15:09:57 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router.sv"                            -work router                                    
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:57 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_router.sv -work router 
# -- Compiling module nios2_system_mm_interconnect_0_router_default_decode
# -- Compiling module nios2_system_mm_interconnect_0_router
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0_router
# End time: 15:09:58 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_avalon_sc_fifo.v"                                             -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:58 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_avalon_sc_fifo.v -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo 
# -- Compiling module altera_avalon_sc_fifo
# 
# Top level modules:
# 	altera_avalon_sc_fifo
# End time: 15:09:58 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv"                                        -work jtag_uart_avalon_jtag_slave_agent         
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:58 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv -work jtag_uart_avalon_jtag_slave_agent 
# -- Compiling module altera_merlin_slave_agent
# ** Warning: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv(618): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv(488): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv(489): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv(490): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv(491): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_agent.sv(34): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# 
# Top level modules:
# 	altera_merlin_slave_agent
# End time: 15:09:58 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 6
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_burst_uncompressor.sv"                                 -work jtag_uart_avalon_jtag_slave_agent         
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:58 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_burst_uncompressor.sv -work jtag_uart_avalon_jtag_slave_agent 
# -- Compiling module altera_merlin_burst_uncompressor
# 
# Top level modules:
# 	altera_merlin_burst_uncompressor
# End time: 15:09:59 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_agent.sv"                                       -work nios2_cpu_data_master_agent               
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:59 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_agent.sv -work nios2_cpu_data_master_agent 
# -- Compiling module altera_merlin_master_agent
# 
# Top level modules:
# 	altera_merlin_master_agent
# End time: 15:09:59 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_translator.sv"                                   -work jtag_uart_avalon_jtag_slave_translator    
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:59 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_slave_translator.sv -work jtag_uart_avalon_jtag_slave_translator 
# -- Compiling module altera_merlin_slave_translator
# 
# Top level modules:
# 	altera_merlin_slave_translator
# End time: 15:09:59 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_translator.sv"                                  -work nios2_cpu_data_master_translator          
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:59 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_translator.sv -work nios2_cpu_data_master_translator 
# -- Compiling module altera_merlin_master_translator
# 
# Top level modules:
# 	altera_merlin_master_translator
# End time: 15:09:59 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v"                                        -work cpu                                       
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:09:59 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v -work cpu 
# -- Compiling module nios2_system_nios2_cpu_cpu_register_bank_a_module
# -- Compiling module nios2_system_nios2_cpu_cpu_register_bank_b_module
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_debug
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_break
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_xbrk
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_dbrk
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_itrace
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_td_mode
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_dtrace
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_compute_input_tm_cnt
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_fifo_wrptr_inc
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_fifo_cnt_inc
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_fifo
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_pib
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci_im
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_performance_monitors
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_avalon_reg
# -- Compiling module nios2_system_nios2_cpu_cpu_ociram_sp_ram_module
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_ocimem
# -- Compiling module nios2_system_nios2_cpu_cpu_nios2_oci
# -- Compiling module nios2_system_nios2_cpu_cpu
# 
# Top level modules:
# 	nios2_system_nios2_cpu_cpu_nios2_performance_monitors
# 	nios2_system_nios2_cpu_cpu
# End time: 15:10:00 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_debug_slave_sysclk.v"                     -work cpu                                       
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:00 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_debug_slave_sysclk.v -work cpu 
# -- Compiling module nios2_system_nios2_cpu_cpu_debug_slave_sysclk
# 
# Top level modules:
# 	nios2_system_nios2_cpu_cpu_debug_slave_sysclk
# End time: 15:10:00 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_debug_slave_tck.v"                        -work cpu                                       
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:00 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_debug_slave_tck.v -work cpu 
# -- Compiling module nios2_system_nios2_cpu_cpu_debug_slave_tck
# 
# Top level modules:
# 	nios2_system_nios2_cpu_cpu_debug_slave_tck
# End time: 15:10:00 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_debug_slave_wrapper.v"                    -work cpu                                       
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:00 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_debug_slave_wrapper.v -work cpu 
# -- Compiling module nios2_system_nios2_cpu_cpu_debug_slave_wrapper
# 
# Top level modules:
# 	nios2_system_nios2_cpu_cpu_debug_slave_wrapper
# End time: 15:10:01 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_test_bench.v"                             -work cpu                                       
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:01 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu_test_bench.v -work cpu 
# -- Compiling module nios2_system_nios2_cpu_cpu_test_bench
# 
# Top level modules:
# 	nios2_system_nios2_cpu_cpu_test_bench
# End time: 15:10:01 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_reset_controller.v"                                           -work rst_controller                            
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:01 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_reset_controller.v -work rst_controller 
# -- Compiling module altera_reset_controller
# 
# Top level modules:
# 	altera_reset_controller
# End time: 15:10:01 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_reset_synchronizer.v"                                         -work rst_controller                            
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:01 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_reset_synchronizer.v -work rst_controller 
# -- Compiling module altera_reset_synchronizer
# 
# Top level modules:
# 	altera_reset_synchronizer
# End time: 15:10:01 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -sv "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_irq_mapper.sv"                                          -work irq_mapper                                
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:01 on Jan 26,2021
# vlog -reportprogress 300 -sv C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_irq_mapper.sv -work irq_mapper 
# -- Compiling module nios2_system_irq_mapper
# 
# Top level modules:
# 	nios2_system_irq_mapper
# End time: 15:10:01 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0.v"                                    -work mm_interconnect_0                         
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:01 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0.v -work mm_interconnect_0 
# -- Compiling module nios2_system_mm_interconnect_0
# 
# Top level modules:
# 	nios2_system_mm_interconnect_0
# End time: 15:10:02 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_pb_pio.vhd"                                             -work pb_pio                                    
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:02 on Jan 26,2021
# vcom -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_pb_pio.vhd -work pb_pio 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package altera_europa_support_lib
# -- Loading package altera_mf_components
# -- Compiling entity nios2_system_pb_pio
# -- Compiling architecture europa of nios2_system_pb_pio
# End time: 15:10:02 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_onchip_memory.vhd"                                      -work onchip_memory                             
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:02 on Jan 26,2021
# vcom -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_onchip_memory.vhd -work onchip_memory 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package altera_europa_support_lib
# -- Loading package altera_mf_components
# -- Compiling entity nios2_system_onchip_memory
# -- Compiling architecture europa of nios2_system_onchip_memory
# End time: 15:10:02 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu.v"                                            -work nios2_cpu                                 
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:02 on Jan 26,2021
# vlog -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu.v -work nios2_cpu 
# -- Compiling module nios2_system_nios2_cpu
# 
# Top level modules:
# 	nios2_system_nios2_cpu
# End time: 15:10:02 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_led_pio.vhd"                                            -work led_pio                                   
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:02 on Jan 26,2021
# vcom -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_led_pio.vhd -work led_pio 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package altera_europa_support_lib
# -- Loading package altera_mf_components
# -- Compiling entity nios2_system_led_pio
# -- Compiling architecture europa of nios2_system_led_pio
# End time: 15:10:03 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_jtag_uart.vhd"                                          -work jtag_uart                                 
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:03 on Jan 26,2021
# vcom -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_jtag_uart.vhd -work jtag_uart 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package altera_europa_support_lib
# -- Loading package altera_mf_components
# -- Compiling entity nios2_system_jtag_uart_sim_scfifo_w
# -- Compiling architecture europa of nios2_system_jtag_uart_sim_scfifo_w
# -- Compiling entity nios2_system_jtag_uart_scfifo_w
# -- Compiling architecture europa of nios2_system_jtag_uart_scfifo_w
# -- Compiling entity nios2_system_jtag_uart_sim_scfifo_r
# -- Compiling architecture europa of nios2_system_jtag_uart_sim_scfifo_r
# -- Compiling entity nios2_system_jtag_uart_scfifo_r
# -- Compiling architecture europa of nios2_system_jtag_uart_scfifo_r
# -- Compiling entity nios2_system_jtag_uart
# -- Compiling architecture europa of nios2_system_jtag_uart
# End time: 15:10:03 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/nios2_system.vhd"                                                                                                               
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:03 on Jan 26,2021
# vcom -reportprogress 300 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/nios2_system.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity nios2_system
# -- Compiling architecture rtl of nios2_system
# End time: 15:10:03 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vcom -93 -work work {C:/intelFPGA_prj/presspb_led_nios2/presspb_led_nios2.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:03 on Jan 26,2021
# vcom -reportprogress 300 -93 -work work C:/intelFPGA_prj/presspb_led_nios2/presspb_led_nios2.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity presspb_led_nios2
# -- Compiling architecture rtl of presspb_led_nios2
# End time: 15:10:03 on Jan 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vcom -93 -work work {C:/intelFPGA_prj/presspb_led_nios2/id113961_testbench.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:10:03 on Jan 26,2021
# vcom -reportprogress 300 -93 -work work C:/intelFPGA_prj/presspb_led_nios2/id113961_testbench.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity testbench
# -- Compiling architecture sim of testbench
# End time: 15:10:04 on Jan 26,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_001 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_003 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L nios2_cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L nios2_cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L pb_pio -L onchip_memory -L nios2_cpu -L led_pio -L jtag_uart -voptargs="+acc"  testbench
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_001 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_003 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L nios2_cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L nios2_cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L pb_pio -L onchip_memory -L nios2_cpu -L led_pio -L jtag_uart -voptargs=""+acc"" testbench 
# Start time: 15:10:04 on Jan 26,2021
# //  ModelSim - Intel FPGA Edition 2020.1 Feb 28 2020
# //
# //  Copyright 1991-2020 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim - Intel FPGA Edition and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.testbench(sim)
# Loading work.presspb_led_nios2(rtl)
# Loading ieee.numeric_std(body)
# Loading work.nios2_system(rtl)
# Loading altera.altera_europa_support_lib(body)
# Loading jtag_uart.nios2_system_jtag_uart(europa)
# Loading jtag_uart.nios2_system_jtag_uart_scfifo_w(europa)
# Loading altera_mf.altera_mf_components
# Loading jtag_uart.nios2_system_jtag_uart_sim_scfifo_w(europa)
# Loading jtag_uart.nios2_system_jtag_uart_scfifo_r(europa)
# Loading jtag_uart.nios2_system_jtag_uart_sim_scfifo_r(europa)
# Loading led_pio.nios2_system_led_pio(europa)
# Loading nios2_cpu.nios2_system_nios2_cpu
# Loading cpu.nios2_system_nios2_cpu_cpu
# Loading cpu.nios2_system_nios2_cpu_cpu_test_bench
# Loading cpu.nios2_system_nios2_cpu_cpu_register_bank_a_module
# Loading altera_mf_ver.altsyncram
# Loading cpu.nios2_system_nios2_cpu_cpu_register_bank_b_module
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_debug
# Loading altera_mf_ver.altera_std_synchronizer
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_break
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_xbrk
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_dbrk
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_itrace
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_dtrace
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_td_mode
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_fifo
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_compute_input_tm_cnt
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_fifo_wrptr_inc
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_fifo_cnt_inc
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_pib
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_oci_im
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_avalon_reg
# Loading cpu.nios2_system_nios2_cpu_cpu_nios2_ocimem
# Loading cpu.nios2_system_nios2_cpu_cpu_ociram_sp_ram_module
# Loading cpu.nios2_system_nios2_cpu_cpu_debug_slave_wrapper
# Loading cpu.nios2_system_nios2_cpu_cpu_debug_slave_tck
# Loading cpu.nios2_system_nios2_cpu_cpu_debug_slave_sysclk
# Loading altera_mf_ver.altsyncram_body
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION
# Loading onchip_memory.nios2_system_onchip_memory(europa)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altsyncram(translated)
# Loading pb_pio.nios2_system_pb_pio(europa)
# Loading mm_interconnect_0.nios2_system_mm_interconnect_0
# Loading sv_std.std
# Loading nios2_cpu_data_master_translator.altera_merlin_master_translator
# Loading jtag_uart_avalon_jtag_slave_translator.altera_merlin_slave_translator
# Loading nios2_cpu_data_master_agent.altera_merlin_master_agent
# Loading jtag_uart_avalon_jtag_slave_agent.altera_merlin_slave_agent
# Loading jtag_uart_avalon_jtag_slave_agent.altera_merlin_burst_uncompressor
# Loading jtag_uart_avalon_jtag_slave_agent_rsp_fifo.altera_avalon_sc_fifo
# Loading router.nios2_system_mm_interconnect_0_router
# Loading router.nios2_system_mm_interconnect_0_router_default_decode
# Loading router_001.nios2_system_mm_interconnect_0_router_001
# Loading router_001.nios2_system_mm_interconnect_0_router_001_default_decode
# Loading router_002.nios2_system_mm_interconnect_0_router_002
# Loading router_002.nios2_system_mm_interconnect_0_router_002_default_decode
# Loading router_003.nios2_system_mm_interconnect_0_router_003
# Loading router_003.nios2_system_mm_interconnect_0_router_003_default_decode
# Loading cmd_demux.nios2_system_mm_interconnect_0_cmd_demux
# Loading cmd_demux_001.nios2_system_mm_interconnect_0_cmd_demux_001
# Loading cmd_mux.nios2_system_mm_interconnect_0_cmd_mux
# Loading cmd_mux_001.nios2_system_mm_interconnect_0_cmd_mux_001
# Loading cmd_mux_001.altera_merlin_arbitrator
# Loading cmd_mux_001.altera_merlin_arb_adder
# Loading rsp_demux.nios2_system_mm_interconnect_0_rsp_demux
# Loading rsp_mux.nios2_system_mm_interconnect_0_rsp_mux
# Loading rsp_mux.altera_merlin_arbitrator
# Loading rsp_mux.altera_merlin_arb_adder
# Loading rsp_mux_001.nios2_system_mm_interconnect_0_rsp_mux_001
# Loading rsp_mux_001.altera_merlin_arbitrator
# Loading rsp_mux_001.altera_merlin_arb_adder
# ** Warning: (vsim-8311) System Verilog assertions are supported only in Questasim.
# Loading avalon_st_adapter.nios2_system_mm_interconnect_0_avalon_st_adapter(rtl)
# Loading error_adapter_0.nios2_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0
# Loading irq_mapper.nios2_system_irq_mapper
# Loading rst_controller.altera_reset_controller
# Loading rst_controller.altera_reset_synchronizer
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'the_altsyncram'.  Expected 23, found 6.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/nios2_cpu/cpu/nios2_system_nios2_cpu_cpu_register_bank_a/the_altsyncram File: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v Line: 50
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'wren_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'rden_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'rden_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'data_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'clocken0'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'clocken1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'clocken2'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'clocken3'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'aclr0'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'byteena_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'byteena_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'addressstall_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'addressstall_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'q_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(50): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'the_altsyncram'.  Expected 23, found 6.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/nios2_cpu/cpu/nios2_system_nios2_cpu_cpu_register_bank_b/the_altsyncram File: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v Line: 116
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'wren_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'rden_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'rden_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'data_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'clocken0'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'clocken1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'clocken2'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'clocken3'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'aclr0'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'byteena_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'byteena_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'addressstall_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'addressstall_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'q_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(116): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (38) for port 'jdo'. The port definition is at: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(987).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/nios2_cpu/cpu/the_nios2_system_nios2_cpu_cpu_nios2_oci/the_nios2_system_nios2_cpu_cpu_nios2_oci_itrace File: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v Line: 2610
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'the_altsyncram'.  Expected 23, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/nios2_cpu/cpu/the_nios2_system_nios2_cpu_cpu_nios2_oci/the_nios2_system_nios2_cpu_cpu_nios2_ocimem/nios2_system_nios2_cpu_cpu_ociram_sp_ram/the_altsyncram File: C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v Line: 2147
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'wren_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'rden_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'rden_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'data_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'address_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'clocken1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'clocken2'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'clocken3'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'aclr0'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'byteena_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'addressstall_a'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'addressstall_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'q_b'.
# ** Warning: (vsim-3722) C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_nios2_cpu_cpu.v(2147): [TFMPC] - Missing connection for port 'eccstatus'.
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run 30 ms
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/pb_pio
# ** Warning: Warning: DONT_CARE value for read_during_write_mode_port_a is not supported in Stratix device family, it might cause incorrect behavioural simulation result
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/onchip_memory/the_altsyncram
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/led_pio
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/jtag_uart
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/jtag_uart/the_nios2_system_jtag_uart_scfifo_r/the_nios2_system_jtag_uart_sim_scfifo_r
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/fpga/nios2/jtag_uart/the_nios2_system_jtag_uart_scfifo_r/the_nios2_system_jtag_uart_sim_scfifo_r
# Warning: DONT_CARE value for read_during_write_mode_port_a is not supported in Stratix device family, it might cause incorrect behavioural simulation result
# Time: 0  Instance: testbench.fpga.nios2.nios2_cpu.cpu.the_nios2_system_nios2_cpu_cpu_nios2_oci.the_nios2_system_nios2_cpu_cpu_nios2_ocimem.nios2_system_nios2_cpu_cpu_ociram_sp_ram.the_altsyncram.m_default.altsyncram_inst
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 3  Instance: /testbench/fpga/nios2/pb_pio
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 1  Instance: /testbench/fpga/nios2/jtag_uart
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 1  Instance: /testbench/fpga/nios2/jtag_uart
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 1  Instance: /testbench/fpga/nios2/led_pio
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 9  Instance: /testbench/fpga/nios2/led_pio
Hello from Nios II !!quit -sim
# End time: 15:45:50 on Jan 26,2021, Elapsed time: 0:35:46
# Errors: 0, Warnings: 66
quit
