m255
K4
z2
!s11e vcom 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/intelFPGA_prj/presspb_led_nios2/simulation/modelsim
Enios2_system_mm_interconnect_0_avalon_st_adapter
Z1 w1611640598
Z2 DPx4 ieee 11 numeric_std 0 22 aU^R8eGcicLcUFIaBQSL>3
Z3 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z4 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 0
R0
Z5 8C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter.vhd
Z6 FC:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter.vhd
l0
L12 1
VUc2Yk78e?^<]Kj=8oe6fh3
!s100 Y0CgKQ]5Fbn6;@L8=d[_k1
Z7 OV;C;2020.1;71
32
Z8 !s110 1611641394
!i10b 1
Z9 !s108 1611641394.000000
Z10 !s90 -reportprogress|300|C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter.vhd|-work|avalon_st_adapter|
!s107 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter.vhd|
!i113 1
Z11 o-work avalon_st_adapter
Z12 tExplicit 1 CvgOpt 0
Artl
R2
R3
R4
DEx4 work 48 nios2_system_mm_interconnect_0_avalon_st_adapter 0 22 Uc2Yk78e?^<]Kj=8oe6fh3
!i122 0
l61
L44 99
VgMTmfEfCR@1MlBo1Wf8kW0
!s100 bM]9R`83P^3FH3aY9[1LX2
R7
32
R8
!i10b 1
R9
R10
Z13 !s107 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_mm_interconnect_0_avalon_st_adapter.vhd|
!i113 1
R11
R12
