m255
K4
z2
!s11e vcom 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/intelFPGA_prj/presspb_led_nios2/simulation/modelsim
Enios2_system
Z1 w1611640578
Z2 DPx4 ieee 11 numeric_std 0 22 aU^R8eGcicLcUFIaBQSL>3
Z3 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z4 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 0
R0
Z5 8C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/nios2_system.vhd
Z6 FC:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/nios2_system.vhd
l0
L9 1
VD?P0P@WICJdLJ:Ri[hMbD3
!s100 ]l]fZCNzQgBOQLajafg4d1
Z7 OV;C;2020.1;71
32
Z8 !s110 1611641403
!i10b 1
Z9 !s108 1611641403.000000
Z10 !s90 -reportprogress|300|C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/nios2_system.vhd|
Z11 !s107 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/nios2_system.vhd|
!i113 1
Z12 tExplicit 1 CvgOpt 0
Artl
R2
R3
R4
DEx4 work 12 nios2_system 0 22 D?P0P@WICJdLJ:Ri[hMbD3
!i122 0
l279
L18 474
VSe4LUYG?e2=7@cnnHA4VI3
!s100 `4RN^YdZ[jMN[6_n@5N8@1
R7
32
R8
!i10b 1
R9
R10
R11
!i113 1
R12
Epresspb_led_nios2
Z13 w1611042471
R3
R4
!i122 1
R0
Z14 8C:/intelFPGA_prj/presspb_led_nios2/presspb_led_nios2.vhd
Z15 FC:/intelFPGA_prj/presspb_led_nios2/presspb_led_nios2.vhd
l0
L4 1
V0zhSS@b2^T0]>aC1h``8k0
!s100 N<]1l5HHWkbi[bMPm4YHz3
R7
31
R8
!i10b 1
R9
Z16 !s90 -reportprogress|300|-93|-work|work|C:/intelFPGA_prj/presspb_led_nios2/presspb_led_nios2.vhd|
Z17 !s107 C:/intelFPGA_prj/presspb_led_nios2/presspb_led_nios2.vhd|
!i113 1
Z18 o-93 -work work
R12
Artl
R3
R4
DEx4 work 17 presspb_led_nios2 0 22 0zhSS@b2^T0]>aC1h``8k0
!i122 1
l29
L14 29
V7>88`47O9QX`KQSl]Xc8X0
!s100 _B84[GKL<QPKFmiMC_kAU3
R7
31
R8
!i10b 1
R9
R16
R17
!i113 1
R18
R12
Etestbench
Z19 w1611112373
Z20 DPx4 ieee 15 std_logic_arith 0 22 [G314=:2zXJ`VORJe1J@Z1
Z21 DPx4 ieee 18 std_logic_unsigned 0 22 ;eZjO2D4ZDz<]0>8AL<ne1
R3
R4
!i122 2
R0
Z22 8C:/intelFPGA_prj/presspb_led_nios2/id113961_testbench.vhd
Z23 FC:/intelFPGA_prj/presspb_led_nios2/id113961_testbench.vhd
l0
L5 1
V:D7`9Mdb8<a;zGVnRBY3c0
!s100 6cIib>D2WkUX?IoKoc@=F1
R7
31
R8
!i10b 1
R9
Z24 !s90 -reportprogress|300|-93|-work|work|C:/intelFPGA_prj/presspb_led_nios2/id113961_testbench.vhd|
!s107 C:/intelFPGA_prj/presspb_led_nios2/id113961_testbench.vhd|
!i113 1
R18
R12
Asim
R20
R21
R3
R4
DEx4 work 9 testbench 0 22 :D7`9Mdb8<a;zGVnRBY3c0
!i122 2
l28
L8 54
Vh=1KDk0d8UV6L>iTEln]61
!s100 kZj<E3=nzTOT@<]c4aVRE0
R7
31
R8
!i10b 1
R9
R24
Z25 !s107 C:/intelFPGA_prj/presspb_led_nios2/id113961_testbench.vhd|
!i113 1
R18
R12
