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!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/intelFPGA_prj/presspb_led_nios2/simulation/modelsim
vnios2_system_jtag_uart
Z1 !s110 1611646811
!i10b 1
!s100 dZORMhlFj77:G6=LIML`01
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
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Z3 VDg1SIo80bB@j0V0VzS_@n1
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Z4 w1611645943
Z5 8C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_jtag_uart.v
Z6 FC:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_jtag_uart.v
!i122 0
L0 331 257
Z7 OV;L;2020.1;71
r1
!s85 0
31
Z8 !s108 1611646810.000000
!s107 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_jtag_uart.v|
Z9 !s90 -reportprogress|300|C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_jtag_uart.v|-work|jtag_uart|
!i113 1
Z10 o-work jtag_uart
Z11 tCvgOpt 0
vnios2_system_jtag_uart_scfifo_r
R1
!i10b 1
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R0
R4
R5
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L0 243 78
R7
r1
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31
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Z12 !s107 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/nios2_system_jtag_uart.v|
R9
!i113 1
R10
R11
vnios2_system_jtag_uart_scfifo_w
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!i10b 1
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L0 78 76
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31
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!i113 1
R10
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vnios2_system_jtag_uart_sim_scfifo_r
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!i10b 1
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R2
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R4
R5
R6
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L0 164 69
R7
r1
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31
R8
R12
R9
!i113 1
R10
R11
vnios2_system_jtag_uart_sim_scfifo_w
R1
!i10b 1
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R2
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R3
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R5
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!i122 0
L0 21 47
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!s85 0
31
R8
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!i113 1
R10
R11
