m255
K4
z2
!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/intelFPGA_prj/presspb_led_nios2/simulation/modelsim
valtera_merlin_master_translator
DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
!s110 1611646805
!i10b 1
!s100 fR3Ff6Pe4h_lQXBchi=m63
!s11b Dg1SIo80bB@j0V0VzS_@n1
I`6ze4C0GhC=DcK`5ob>PJ3
VDg1SIo80bB@j0V0VzS_@n1
S1
R0
w1611645960
8C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_translator.sv
FC:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_translator.sv
!i122 0
L0 32 525
OV;L;2020.1;71
r1
!s85 0
31
!s108 1611646805.000000
!s107 C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_translator.sv|
!s90 -reportprogress|300|-sv|C:/intelFPGA_prj/presspb_led_nios2/nios2_system/simulation/submodules/altera_merlin_master_translator.sv|-work|nios2_cpu_data_master_translator|
!i113 1
o-sv -work nios2_cpu_data_master_translator
tCvgOpt 0
