// xcvr_sample_tb.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module xcvr_sample_tb (
	);

//	wire    xcvr_sample_inst_clk_100m_bfm_clk_clk;  // xcvr_sample_inst_clk_100m_bfm:clk -> [xcvr_sample_inst:clk_100m_clk, xcvr_sample_inst_reset_bfm:clk]
//	wire    xcvr_sample_inst_clk_156m_bfm_clk_clk;  // xcvr_sample_inst_clk_156m_bfm:clk -> xcvr_sample_inst:clk_156m_clk
//	wire    xcvr_sample_inst_reset_bfm_reset_reset; // xcvr_sample_inst_reset_bfm:reset -> xcvr_sample_inst:reset_reset

    wire       clk_100m_clk;
    wire       clk_156m_clk;
    wire       reset_reset;

    wire       ninit_done;
    wire       xcvr_tx_ready;
    wire       xcvr_rx_ready;
    wire       o_tx_serial_data;
    wire       o_tx_serial_data_n;
    wire       i_rx_serial_data;
    wire       i_rx_serial_data_n;
    wire[79:0] i_tx_parallel_data;
    wire[79:0] o_rx_parallel_data;
    wire       rx_clkout_clk;
    wire       tx_clkout_clk;

    reg [1:0]  s_xcvr_tx_ready_2r;
    reg [9:0]  s_cnt_10b;
    wire       rcvd_data_valid;
    wire[31:0] rcvd_data_32b_hi;
    wire[31:0] rcvd_data_32b_lo;
    
    xcvr_sample_inst_clk_100m_bfm_ip #(.CLOCK_RATE(100000000)) xcvr_sample_inst_clk_100m_bfm (
        .clk (clk_100m_clk)  //  output,  width = 1, clk.clk
    );

    xcvr_sample_inst_clk_156m_bfm_ip #(.CLOCK_RATE(156250000))  xcvr_sample_inst_clk_156m_bfm (
        .clk (clk_156m_clk)  //  output,  width = 1, clk.clk
    );

    xcvr_sample_inst_reset_bfm_ip xcvr_sample_inst_reset_bfm (
        .reset (reset_reset), //  output,  width = 1, reset.reset
        .clk   (clk_100m_clk)   //   input,  width = 1,   clk.clk
    );


     xcvr_sample xcvr_sample_inst (
        .clk_100m_clk                                  (clk_100m_clk),
        .clk_156m_clk                                  (clk_156m_clk),
        .phy_i_tx_reset_tx_reset                       (ninit_done),
        .phy_i_rx_reset_rx_reset                       (ninit_done),
        .phy_o_tx_reset_ack_tx_reset_ack               (),
        .phy_o_rx_reset_ack_rx_reset_ack               (),
        .phy_o_tx_ready_tx_ready                       (xcvr_tx_ready),
        .phy_o_rx_ready_rx_ready                       (xcvr_rx_ready),
        .phy_o_tx_serial_data_o_tx_serial_data         (o_tx_serial_data),
        .phy_o_tx_serial_data_n_o_tx_serial_data_n     (o_tx_serial_data_n),
        .phy_i_rx_serial_data_i_rx_serial_data         (i_rx_serial_data),
        .phy_i_rx_serial_data_n_i_rx_serial_data_n     (i_rx_serial_data_n),
        .phy_o_tx_pll_locked_o_tx_pll_locked           (),
        .phy_o_rx_is_lockedtodata_o_rx_is_lockedtodata (),
        .phy_o_rx_is_lockedtoref_o_rx_is_lockedtoref   (),
        .phy_i_tx_parallel_data_i_tx_parallel_data     (i_tx_parallel_data),
        .phy_o_rx_parallel_data_o_rx_parallel_data     (o_rx_parallel_data),
        .reset_reset                                   (reset_reset),
        .reset_release_ninit_done_ninit_done           (ninit_done),
        .rx_clkout_clk                                 (rx_clkout_clk),
        .tx_clkout_clk                                 (tx_clkout_clk)
    );
    
///////////////////////////////////////////////////////////////////
//// loopback ////
assign i_rx_serial_data   = o_tx_serial_data;
assign i_rx_serial_data_n = o_tx_serial_data_n;

///////////////////////////////////////////////////////////////////
//// tx parallel data ////

always@(posedge tx_clkout_clk or posedge reset_reset) begin
    if (reset_reset)
        s_xcvr_tx_ready_2r <= 2'h0 ;
    else
        s_xcvr_tx_ready_2r <= {s_xcvr_tx_ready_2r[0], xcvr_tx_ready} ;
end

assign s_xcvr_tx_ready = s_xcvr_tx_ready_2r[1];

always@(posedge tx_clkout_clk or negedge s_xcvr_tx_ready) begin
    if (~s_xcvr_tx_ready)
        s_cnt_10b <= 10'h000 ;
    else
        s_cnt_10b <= s_cnt_10b + 10'h001 ;
end

//// assign tx parallel data ////
assign i_tx_parallel_data[79:72] = 8'h80;
assign i_tx_parallel_data[71:40] = {s_cnt_10b[3:0], s_cnt_10b, s_cnt_10b, s_cnt_10b[9:2]};
assign i_tx_parallel_data[39:32] = 8'h40;
assign i_tx_parallel_data[31: 0] = {s_cnt_10b[1:0], s_cnt_10b, s_cnt_10b, s_cnt_10b};

///////////////////////////////////////////////////////////////////
//// rx parallel data ////

assign rcvd_data_valid  = o_rx_parallel_data[38];
assign rcvd_data_32b_hi = o_rx_parallel_data[71:40];
assign rcvd_data_32b_lo = o_rx_parallel_data[31:0];

endmodule