{ "Info" "IDMS_INIT_MSG_DB" "" "Initialized Quartus Message Database" {  } {  } 0 21958 "Initialized Quartus Message Database" 0 0 "Design Software" 0 -1 0 ""}
{ "Info" "0" "" "Analyzing source files" {  } {  } 0 0 "Analyzing source files" 0 0 "0" 0 0 1756683914097 ""}
{ "Info" "0" "" "Elaborating from top-level entity \"sample\"" {  } {  } 0 0 "Elaborating from top-level entity \"sample\"" 0 0 "0" 0 0 1756683931825 ""}
{ "Info" "IVRFX2_USER_LIBRARY_SEARCH_ORDER" "altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_sc_fifo_1932; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; altera_reset_controller_1924; altera_jtag_avalon_master_191; jtagavmm; altera_iopll_2000; pll; altera_s10_user_rst_clkgate_1949; reset_release " "Library search order is as follows: \"altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_sc_fifo_1932; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; altera_reset_controller_1924; altera_jtag_avalon_master_191; jtagavmm; altera_iopll_2000; pll; altera_s10_user_rst_clkgate_1949; reset_release\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." {  } {  } 0 18235 "Library search order is as follows: \"%1!s!\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." 0 0 "Design Software" 0 -1 1756683931896 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index=\"YES\",sld_node_info_internal=203451904)(1,1)(1,3) rtl sld_jtag_endpoint_adapter.vhd(96) " "VHDL info at sld_jtag_endpoint_adapter.vhd(96): executing entity \"sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index=\"YES\",sld_node_info_internal=203451904)(1,1)(1,3)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 96 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935873 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1) rtl altera_sld_agent_endpoint.vhd(122) " "VHDL info at altera_sld_agent_endpoint.vhd(122): executing entity \"altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935874 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=5,receive_width=26,settings=\"\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host \{ \} type_name 0 instance_name 0 psig 9b67919e\}\")(1,155) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=5,receive_width=26,settings=\"\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host \{ \} type_name 0 instance_name 0 psig 9b67919e\}\")(1,155)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935875 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(126) " "Verilog HDL info at jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(126): extracting RAM for identifier 'mem'" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" 126 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1756683935892 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(127) " "Verilog HDL info at jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1756683935892 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 jtagavmm_channel_adapter_1922_rd56ufy.sv(91) " "Verilog HDL assignment warning at jtagavmm_channel_adapter_1922_rd56ufy.sv(91): truncated value with size 8 to match size of target (1)" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/channel_adapter_1922/synth/jtagavmm_channel_adapter_1922_rd56ufy.sv" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/channel_adapter_1922/synth/jtagavmm_channel_adapter_1922_rd56ufy.sv" 91 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1756683935905 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 32 avmm_if.v(128) " "Verilog HDL assignment warning at avmm_if.v(128): truncated value with size 33 to match size of target (32)" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/rtl/avmm_if.v" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/rtl/avmm_if.v" 128 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1756683935908 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_agilex_config_reset_release_endpoint rtl altera_agilex_config_reset_release_endpoint.vhd(122) " "VHDL info at altera_agilex_config_reset_release_endpoint.vhd(122): executing entity \"altera_agilex_config_reset_release_endpoint\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935910 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935911 ""}
{ "Info" "0" "" "Found 47 design entities" {  } {  } 0 0 "Found 47 design 