{ "Info" "IDMS_INIT_MSG_DB" "" "Initialized Quartus Message Database" {  } {  } 0 21958 "Initialized Quartus Message Database" 0 0 "Design Software" 0 -1 0 ""}
{ "Info" "0" "" "Analyzing source files" {  } {  } 0 0 "Analyzing source files" 0 0 "0" 0 0 1756683914097 ""}
{ "Info" "0" "" "Elaborating from top-level entity \"sample\"" {  } {  } 0 0 "Elaborating from top-level entity \"sample\"" 0 0 "0" 0 0 1756683931825 ""}
{ "Info" "IVRFX2_USER_LIBRARY_SEARCH_ORDER" "altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_sc_fifo_1932; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; altera_reset_controller_1924; altera_jtag_avalon_master_191; jtagavmm; altera_iopll_2000; pll; altera_s10_user_rst_clkgate_1949; reset_release " "Library search order is as follows: \"altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_sc_fifo_1932; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; altera_reset_controller_1924; altera_jtag_avalon_master_191; jtagavmm; altera_iopll_2000; pll; altera_s10_user_rst_clkgate_1949; reset_release\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." {  } {  } 0 18235 "Library search order is as follows: \"%1!s!\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." 0 0 "Design Software" 0 -1 1756683931896 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index=\"YES\",sld_node_info_internal=203451904)(1,1)(1,3) rtl sld_jtag_endpoint_adapter.vhd(96) " "VHDL info at sld_jtag_endpoint_adapter.vhd(96): executing entity \"sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index=\"YES\",sld_node_info_internal=203451904)(1,1)(1,3)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 96 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935873 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1) rtl altera_sld_agent_endpoint.vhd(122) " "VHDL info at altera_sld_agent_endpoint.vhd(122): executing entity \"altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935874 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=5,receive_width=26,settings=\"\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host \{ \} type_name 0 instance_name 0 psig 9b67919e\}\")(1,155) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=5,receive_width=26,settings=\"\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host \{ \} type_name 0 instance_name 0 psig 9b67919e\}\")(1,155)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935875 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(126) " "Verilog HDL info at jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(126): extracting RAM for identifier 'mem'" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" 126 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1756683935892 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(127) " "Verilog HDL info at jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/altera_avalon_sc_fifo_1932/synth/jtagavmm_altera_avalon_sc_fifo_1932_onpcouq.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1756683935892 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 jtagavmm_channel_adapter_1922_rd56ufy.sv(91) " "Verilog HDL assignment warning at jtagavmm_channel_adapter_1922_rd56ufy.sv(91): truncated value with size 8 to match size of target (1)" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/channel_adapter_1922/synth/jtagavmm_channel_adapter_1922_rd56ufy.sv" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/jtagavmm/channel_adapter_1922/synth/jtagavmm_channel_adapter_1922_rd56ufy.sv" 91 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1756683935905 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 32 avmm_if.v(128) " "Verilog HDL assignment warning at avmm_if.v(128): truncated value with size 33 to match size of target (32)" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/rtl/avmm_if.v" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/rtl/avmm_if.v" 128 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1756683935908 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_agilex_config_reset_release_endpoint rtl altera_agilex_config_reset_release_endpoint.vhd(122) " "VHDL info at altera_agilex_config_reset_release_endpoint.vhd(122): executing entity \"altera_agilex_config_reset_release_endpoint\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935910 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683935911 ""}
{ "Info" "0" "" "Found 47 design entities" {  } {  } 0 0 "Found 47 design entities" 0 0 "0" 0 0 1756683938699 ""}
{ "Info" "0" "" "There are 50 partitions after elaboration." {  } {  } 0 0 "There are 50 partitions after elaboration." 0 0 "0" 0 0 1756683938827 ""}
{ "Info" "" "Running rule checking for Agilex5 protocol IPs... " "Running rule checking for Agilex5 protocol IPs..." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1756683939450 ""}
{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab_0 " "Starting IP generation for the debug fabric: alt_sld_fab_0." {  } {  } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Design Software" 0 -1 1756683939869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Quartus is a registered trademark of Intel Corporation in the " "Quartus is a registered trademark of Intel Corporation in the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "US and other countries.  Portions of the Quartus Prime software " "US and other countries.  Portions of the Quartus Prime software" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Code, and other portions of the code included in this download " "Code, and other portions of the code included in this download" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Or on this DVD, are licensed to Intel Corporation and are the " "Or on this DVD, are licensed to Intel Corporation and are the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Copyrighted property of third parties. For license details, " "Copyrighted property of third parties. For license details," {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Refer to the End User License Agreement at " "Refer to the End User License Agreement at" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Http://fpgasoftware.intel.com/eula. " "Http://fpgasoftware.intel.com/eula." {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683940229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent " "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949084 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949084 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949084 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949084 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949084 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949084 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949085 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949085 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949085 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949085 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949085 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949085 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949085 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949099 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949099 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949099 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949099 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949099 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949099 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 2 " "Set_instance_parameter_value sldfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949100 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52 " "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 2 " "Set_instance_parameter_value configresetfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock " "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit " "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_0 clock " "Add_connection sldfabric.clock_1 splitter.clock_0 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_0 conduit " "Add_connection sldfabric.node_1 splitter.node_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683949101 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent " "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951211 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951212 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951213 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951213 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 2 " "Set_instance_parameter_value sldfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52 " "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 2 " "Set_instance_parameter_value configresetfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951230 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock " "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit " "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_0 clock " "Add_connection sldfabric.clock_1 splitter.clock_0 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_0 conduit " "Add_connection sldfabric.node_1 splitter.node_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951231 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951461 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Deploying alt_sld_fab_0 to D:\\1_sample_a3\\1_sample_atum\\0_iopll\\sample_rev0\\dni\\sandboxes\\HD10568D_2948_0\\sld\\ipgen\\alt_sld_fab_0.ip " "Deploying alt_sld_fab_0 to D:\\1_sample_a3\\1_sample_atum\\0_iopll\\sample_rev0\\dni\\sandboxes\\HD10568D_2948_0\\sld\\ipgen\\alt_sld_fab_0.ip" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683951491 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Quartus is a registered trademark of Intel Corporation in the " "Quartus is a registered trademark of Intel Corporation in the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "US and other countries.  Portions of the Quartus Prime software " "US and other countries.  Portions of the Quartus Prime software" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Code, and other portions of the code included in this download " "Code, and other portions of the code included in this download" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Or on this DVD, are licensed to Intel Corporation and are the " "Or on this DVD, are licensed to Intel Corporation and are the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Copyrighted property of third parties. For license details, " "Copyrighted property of third parties. For license details," {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Refer to the End User License Agreement at " "Refer to the End User License Agreement at" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Http://fpgasoftware.intel.com/eula. " "Http://fpgasoftware.intel.com/eula." {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953665 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683953666 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent " "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965151 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965151 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965151 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965151 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965152 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965152 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965166 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 2 " "Set_instance_parameter_value sldfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52 " "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 2 " "Set_instance_parameter_value configresetfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965167 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock " "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit " "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_0 clock " "Add_connection sldfabric.clock_1 splitter.clock_0 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_0 conduit " "Add_connection sldfabric.node_1 splitter.node_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683965168 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent " "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967102 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967103 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967103 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967117 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967142 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967143 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967143 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 2 " "Set_instance_parameter_value sldfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967148 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52 " "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 2 " "Set_instance_parameter_value configresetfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967149 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock " "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit " "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_0 clock " "Add_connection sldfabric.clock_1 splitter.clock_0 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_0 conduit " "Add_connection sldfabric.node_1 splitter.node_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967150 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Saving generation log to D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/dni/sandboxes/HD10568D_2948_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt " "Saving generation log to D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/dni/sandboxes/HD10568D_2948_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967525 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Generated by version: 25.1.1 build 125 " "Generated by version: 25.1.1 build 125" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967525 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Starting: Create HDL design files for synthesis " "Starting: Create HDL design files for synthesis" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967541 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Qsys-generate D:\\1_sample_a3\\1_sample_atum\\0_iopll\\sample_rev0\\dni\\sandboxes\\HD10568D_2948_0\\sld\\ipgen\\alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=D:\\1_sample_a3\\1_sample_atum\\0_iopll\\sample_rev0\\dni\\sandboxes\\HD10568D_2948_0\\sld\\ipgen\\alt_sld_fab_0 --family=\"Agilex 3\" --part=A3CZ135BB18AE7S " "Qsys-generate D:\\1_sample_a3\\1_sample_atum\\0_iopll\\sample_rev0\\dni\\sandboxes\\HD10568D_2948_0\\sld\\ipgen\\alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=D:\\1_sample_a3\\1_sample_atum\\0_iopll\\sample_rev0\\dni\\sandboxes\\HD10568D_2948_0\\sld\\ipgen\\alt_sld_fab_0 --family=\"Agilex 3\" --part=A3CZ135BB18AE7S" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683967541 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent " "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968063 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968064 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968064 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968064 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968064 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968064 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968065 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 2 " "Set_instance_parameter_value sldfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968066 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52 " "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 2 " "Set_instance_parameter_value configresetfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock " "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit " "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_0 clock " "Add_connection sldfabric.clock_1 splitter.clock_0 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_0 conduit " "Add_connection sldfabric.node_1 splitter.node_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968067 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968068 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent " "Add_instance auto_signaltap_auto_signaltap_0 altera_signaltap_agent" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968206 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 PREFER_HOST \{\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 TYPE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 INSTANCE_NAME \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_BLOCK_TYPE \{AUTO\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_DATA_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_BITS \{31\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_NODE_INFO \{805334528\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_POWER_UP_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK \{000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INVERSION_MASK_LENGTH \{117\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968228 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968229 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SEGMENT_SIZE \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968237 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ATTRIBUTE_MEM_MODE \{OFF\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968237 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_FLOW_USE_GENERATED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968237 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_STATE_BITS \{11\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968237 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_BUFFER_FULL_STOP \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968237 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_CURRENT_RESOURCE_WIDTH \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968237 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_INCREMENTAL_ROUTING \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968237 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SAMPLE_DEPTH \{1024\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_IN_ENABLED \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_RAM_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_COUNTER_PIPELINE \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ADVANCED_TRIGGER_ENTITY \{basic,1,\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_TRIGGER_LEVEL_PIPELINE \{1\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_ENABLE_ADVANCED_TRIGGER \{0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\} " "Set_instance_parameter_value auto_signaltap_auto_signaltap_0 SLD_SECTION_ID \{auto_signaltap_0\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 2 " "Set_instance_parameter_value sldfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968238 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52 " "Set_instance_parameter_value ident DESIGN_HASH be1384c8e6de4901fd52" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 2 " "Set_instance_parameter_value configresetfabric COUNT 2" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968239 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_0\} \} moduleassign \{debug.virtualInterface.link_0 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock " "Add_connection sldfabric.clock_0 auto_signaltap_auto_signaltap_0.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit " "Add_connection sldfabric.node_0 auto_signaltap_auto_signaltap_0.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_0 clock " "Add_connection sldfabric.clock_1 splitter.clock_0 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_0 conduit " "Add_connection sldfabric.node_1 splitter.node_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 auto_signaltap_auto_signaltap_0.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_1 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_1 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968240 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968428 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Transforming system: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Transforming system: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968583 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Naming system components in system: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Naming system components in system: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968790 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Processing generation queue\" " "Alt_sld_fab_0: \"Processing generation queue\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968798 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968798 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968838 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_1920_xouzyqi\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_1920_xouzyqi\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683968982 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: altera_signaltap_agent_wrapper\" " "Alt_sld_fab_0: \"Generating: altera_signaltap_agent_wrapper\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969293 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_splitter_1920_wfgso7q\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_splitter_1920_wfgso7q\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969340 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: altera_jtag_wys_atom\" " "Alt_sld_fab_0: \"Generating: altera_jtag_wys_atom\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969420 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969514 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_connection_identification_hub_1920_5m4ydra\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_connection_identification_hub_1920_5m4ydra\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969624 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_configuration_debug_reset_release_hub_203_wuwp3pa\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_configuration_debug_reset_release_hub_203_wuwp3pa\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969687 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Conf_reset_src: \"Generating: conf_reset_src\" " "Conf_reset_src: \"Generating: conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Grounded_conf_reset_src: \"Generating: grounded_conf_reset_src\" " "Grounded_conf_reset_src: \"Generating: grounded_conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_cpztvzi\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_cpztvzi\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: conf_reset_src\" " "Alt_sld_fab_0: \"Generating: conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969749 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: grounded_conf_reset_src\" " "Alt_sld_fab_0: \"Generating: grounded_conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969811 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_for_debug\" " "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_for_debug\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969826 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_to_debug_logic\" " "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_to_debug_logic\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969856 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: Done \"alt_sld_fab_0\" with 14 modules, 16 files " "Alt_sld_fab_0: Done \"alt_sld_fab_0\" with 14 modules, 16 files" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683969871 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Finished: Create HDL design files for synthesis " "Finished: Create HDL design files for synthesis" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683970107 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Generation of D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/dni/sandboxes/HD10568D_2948_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 2678 ms " "Generation of D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/dni/sandboxes/HD10568D_2948_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 2678 ms" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1756683970107 ""}
{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab_0 " "Finished IP generation for the debug fabric: alt_sld_fab_0." {  } {  } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Design Software" 0 -1 1756683970893 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_signaltap(sld_node_info=805334528,sld_section_id=\"auto_signaltap_0\",sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_trigger_level=1,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_current_resource_width=1,sld_create_monitor_interface=1,sld_use_jtag_signal_adapter=0)(1,13)(1,16)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5) rtl sld_signaltap.vhd(39) " "VHDL info at sld_signaltap.vhd(39): executing entity \"sld_signaltap(sld_node_info=805334528,sld_section_id=\"auto_signaltap_0\",sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_trigger_level=1,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_current_resource_width=1,sld_create_monitor_interface=1,sld_use_jtag_signal_adapter=0)(1,13)(1,16)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_signaltap.vhd" 39 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976859 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_signaltap_impl(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_trigger_level=1,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_current_resource_width=1,sld_trigger_pipeline=0,sld_ram_pipeline=0,sld_counter_pipeline=0)(1,13)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5) rtl sld_signaltap_impl.vhd(167) " "VHDL info at sld_signaltap_impl.vhd(167): executing entity \"sld_signaltap_impl(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_trigger_level=1,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_current_resource_width=1,sld_trigger_pipeline=0,sld_ram_pipeline=0,sld_counter_pipeline=0)(1,13)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 167 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976863 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_signaltap_jtag(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5) rtl sld_signaltap_impl.vhd(522) " "VHDL info at sld_signaltap_impl.vhd(522): executing entity \"sld_signaltap_jtag(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 522 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976866 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_stp_acq_core(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(9,0)(9,0)(9,0)(20,0)(0,0)(16,0)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5) rtl sld_stp_acq_core.vhd(117) " "VHDL info at sld_stp_acq_core.vhd(117): executing entity \"sld_stp_acq_core(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(9,0)(9,0)(9,0)(20,0)(0,0)(16,0)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_acq_core.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_acq_core.vhd" 117 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976873 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_ela_control(ip_major_version=6,trigger_input_width=31,advanced_trigger_entity=\"basic,1,\",mem_address_bits=10,sample_depth=1024,state_bits=11,segment_size_bits=10,state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",storage_qualifier_inversion_mask_length=0,storage_qualifier_advanced_condition_entity=\"basic\")(1,8)(116,116)(1,25)(1,3)(1,5) rtl sld_ela_control.vhd(72) " "VHDL info at sld_ela_control.vhd(72): executing entity \"sld_ela_control(ip_major_version=6,trigger_input_width=31,advanced_trigger_entity=\"basic,1,\",mem_address_bits=10,sample_depth=1024,state_bits=11,segment_size_bits=10,state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",storage_qualifier_inversion_mask_length=0,storage_qualifier_advanced_condition_entity=\"basic\")(1,8)(116,116)(1,25)(1,3)(1,5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_ela_control.vhd" 72 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976876 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_ela_basic_multi_level_trigger(ip_major_version=6,data_bits=31)(0,0) rtl sld_ela_control.vhd(1174) " "VHDL info at sld_ela_control.vhd(1174): executing entity \"sld_ela_basic_multi_level_trigger(ip_major_version=6,data_bits=31)(0,0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_ela_control.vhd" 1174 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976878 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_mbpmg(ip_major_version=6,data_bits=31) rtl sld_mbpmg.vhd(37) " "VHDL info at sld_mbpmg.vhd(37): executing entity \"sld_mbpmg(ip_major_version=6,data_bits=31)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_mbpmg.vhd" 37 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976880 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_sbpmg(ip_major_version=6) rtl sld_mbpmg.vhd(257) " "VHDL info at sld_mbpmg.vhd(257): executing entity \"sld_sbpmg(ip_major_version=6)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_mbpmg.vhd" 257 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976881 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_ela_trigger_flow_mgr(ip_major_version=6,trigger_level=1,segment_size_bits=10)(0,0) rtl sld_ela_trigger_flow_mgr.vhd(10) " "VHDL info at sld_ela_trigger_flow_mgr.vhd(10): executing entity \"sld_ela_trigger_flow_mgr(ip_major_version=6,trigger_level=1,segment_size_bits=10)(0,0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 10 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976884 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_buffer_manager(ip_major_version=6,address_bits=10,segment_size_bits=10,num_segments_bits=1)(1,3) rtl sld_buffer_manager.vhd(47) " "VHDL info at sld_buffer_manager.vhd(47): executing entity \"sld_buffer_manager(ip_major_version=6,address_bits=10,segment_size_bits=10,num_segments_bits=1)(1,3)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 47 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976887 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_stp_comm_acq_domain_xing(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(9,0)(20,0)(0,0)(16,0)(9,0)(9,0)(9,0)(9,0)(9,0)(20,0)(0,0)(16,0)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5) rtl sld_stp_comm_acq_domain_xing.vhd(21) " "VHDL info at sld_stp_comm_acq_domain_xing.vhd(21): executing entity \"sld_stp_comm_acq_domain_xing(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(9,0)(20,0)(0,0)(16,0)(9,0)(9,0)(9,0)(9,0)(9,0)(20,0)(0,0)(16,0)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_comm_acq_domain_xing.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_comm_acq_domain_xing.vhd" 21 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976896 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "intel_stp_status_bits_cdc(stp_status_bits_width=17) rtl intel_stp_status_bits_cdc.vhd(26) " "VHDL info at intel_stp_status_bits_cdc.vhd(26): executing entity \"intel_stp_status_bits_cdc(stp_status_bits_width=17)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/intel_stp_status_bits_cdc.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/intel_stp_status_bits_cdc.vhd" 26 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976903 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_stp_comm_jtag(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(9,0)(9,0)(9,0)(20,0)(0,0)(16,0)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5) rtl sld_stp_comm_jtag.vhd(16) " "VHDL info at sld_stp_comm_jtag.vhd(16): executing entity \"sld_stp_comm_jtag(sld_data_bits=31,sld_trigger_bits=31,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=1024,sld_segment_size=1024,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_in_enabled=0,sld_advanced_trigger_entity=\"basic,1,\",sld_inversion_mask_length=117,sld_inversion_mask=\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",sld_state_flow_mgr_entity=\"state_flow_mgr_entity.vhd\",sld_current_resource_width=1)(9,0)(9,0)(9,0)(20,0)(0,0)(16,0)(1,4)(1,8)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,116)(1,25)(1,3)(1,3)(1,5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_comm_jtag.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_comm_jtag.vhd" 16 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976908 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_offload_buffer_mgr(ip_major_version=6,buffer_depth=1024,segment_count=1,mem_address_bits=10,data_bits=31,status_bits=21,data_bit_cntr_bits=5,status_bit_cntr_bits=5,ela_status_bits=4) rtl sld_buffer_manager.vhd(563) " "VHDL info at sld_buffer_manager.vhd(563): executing entity \"sld_offload_buffer_mgr(ip_major_version=6,buffer_depth=1024,segment_count=1,mem_address_bits=10,data_bits=31,status_bits=21,data_bit_cntr_bits=5,status_bit_cntr_bits=5,ela_status_bits=4)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 563 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976912 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_rom_sr INFO_REG sld_rom_sr.vhd(5) " "VHDL info at sld_rom_sr.vhd(5): executing entity \"sld_rom_sr\" with architecture \"INFO_REG\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_rom_sr.vhd" 5 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976919 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "serial_crc_16 rtl sld_stp_comm_jtag.vhd(849) " "VHDL info at sld_stp_comm_jtag.vhd(849): executing entity \"serial_crc_16\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_comm_jtag.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_stp_comm_jtag.vhd" 849 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976948 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq(device_family=\"Agilex 3\",count=2,n_node_ir_bits=10,node_info=\"0000110000100000011011100000000000110000000000000110111000000000\",compilation_mode=0,force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=3)(1,8)(1,0)(1,64) rtl alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq.vhd(13) " "VHDL info at alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq.vhd(13): executing entity \"alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq(device_family=\"Agilex 3\",count=2,n_node_ir_bits=10,node_info=\"0000110000100000011011100000000000110000000000000110111000000000\",compilation_mode=0,force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=3)(1,8)(1,0)(1,64)\" with architecture \"rtl\"" {  } { { "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/dni/sandboxes/HD10568D_2948_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq.vhd" "" { Text "D:/1_sample_a3/1_sample_atum/0_iopll/sample_rev0/dni/sandboxes/HD10568D_2948_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_zkxtliq.vhd" 13 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976963 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_hub(device_family=\"Agilex 3\",n_nodes=2,n_node_ir_bits=10,node_info=\"0000110000100000011011100000000000110000000000000110111000000000\",force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=3)(1,8)(63,0) rtl sld_jtag_hub.vhd(89) " "VHDL info at sld_jtag_hub.vhd(89): executing entity \"sld_jtag_hub(device_family=\"Agilex 3\",n_nodes=2,n_node_ir_bits=10,node_info=\"0000110000100000011011100000000000110000000000000110111000000000\",force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=3)(1,8)(63,0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 89 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1756683976965 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_shadow_jsm(ip_major_version=1,ip_minor_version=5) rtl sld_hub.vhd(1554) " "VHDL info at sld_hub.vhd(1554): executing entity \"sld_shadow_jsm(ip_major_version=1,ip_minor_version=5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_hub.vhd" 1554 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software"