1. Introduction
This article provides a sample bare-metal application for Agilex™ 7 FPGAs and describes how to run the application in a non-OS environment.
2. Sample bare-metal application offerings/contents
This article provides a sample bare-metal application.
Attached file name : Baremetal_HelloWorld_v0.tar.gz
Please refer to Chapter 3 for the execution procedure.
This sample is simple and outputs "Hello World!".
The source file name displaying "Hellow World!" is hwlib.c file.
3. Execution method
This section describes how to run the debugger and from the SD card, respectively.
Note:
Both execution methods require booting to the console after the boot loader is started.
Please refer to the following web page for instructions on how to create an environment.
GHRD Linux Boot Examples - Altera FPGA Developer Site
[Supplemental]
Please confirm either "Booting From SDCard" or "Boot from QSPI" depending on the type of Flush. In this contents, booting from SD card is used.
To start booting HPS, you need to write .sof file to SDM (Secure Device Manager) via JTAG or write .jic file to QSPI Flash for configuration in advance.
Please also check the following article for Agilex boot flow.
Stratix® 10 FPGA/Agilex™ 7 FPGA Boot Method and Configuration
3-1. Run from the debugger
The configuration is shown in the figure below (Figure 1).
Boot the boot loader beforehand and run it from the debugger (e.g. Arm DS).
The procedure for executing from the debugger is described in 3-1-1.
[Figure 1] Configuration when executing from the debugger
3-1-1. Build the Bare Metal application
Import and build the bare-metal application attached to this article.
Please refer to Figure 2 and Figure 3 for importing and building.
[Figure 2] Import Procedure
[Figure 3] Building a bare-metal application
3-1-2. Executing Bare Metal application
Right-click on the project and select [Debug As] -> [Debug Configuration] to run debugging, as shown in the figure below (Figure 4).
[Figure 4] Executing Debugging of bare-metal application
3-1-3. Checking the Log
When the build is successfully completed, the following log will be output.
U-Boot SPL 2022.01 (Sep 08 2022 - 22:48:40 +0900)
Reset state: Cold
MPU 1200000 kHz
L4 Main 400000 kHz
L4 sys free 100000 kHz
L4 MP 200000 kHz
L4 SP 100000 kHz
SDMMC 50000 kHz
DDR: 8192 MiB
SDRAM-ECC: Initialized success with 1728 ms
QSPI: Reference clock at 400000 kHz
WDT: Started watchdog@ffd00200 with servicing (10s timeout)
Trying to boot from MMC1
## Checking hash(es) for config board-0 ... OK
## Checking hash(es) for Image atf ... crc32+ OK
## Checking hash(es) for Image uboot ... crc32+ OK
## Checking hash(es) for Image fdt-0 ... crc32+ OK
NOTICE: BL31: v2.6.1(release):
NOTICE: BL31: Built : 00:44:55, Jul 28 2022
NOTICE: BL31 CLK freq = 400 MHz
U-Boot 2022.01 (Jul 28 2022 - 00:46:38 + 0900)socfpga_agilex
CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex SoCDK
DRAM: 8 GiB
WDT: Started watchdog@ffd00200 with servicing (10s timeout)
MMC: dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... In: serial0@ffc02000
Out: serial0@ffc02000
Err: serial0@ffc02000
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 12:98:a6:74:4c :bc
eth0: ethernet@ff800000
Hit any key to stop autoboot: 0
SOCFPGA_AGILEX # <- (Bootloader is started and application is executed by debugger in this state)
SOCFPGA_AGILEX # Hello World! <- (Output display of the result of running the bare-metal application
in the debugger)
3-2. Stand-alone execution from SD card
The configuration is shown in the figure below (Figure 5).
The boot loader is started beforehand, and the application is executed from the SD card.
The procedure for executing from the SD card is described in 3-2-1 and later.
[Figure 5] Configuration when executing from the SD card
3-2-1. Build Bare Metal Application
Please refer to "3-1-1. Build the Bare Metal Application".
3-2-2. Store the .bin file generated by the build in the FAT area of the SD card.
After the build process, a sample_app.bin file will be generated in the project (Figure 6).
Store this file in the FAT area of the SD card.
[Figure 6] Binary file to be stored in the SD card
3-2-3. Running Bare Metal application from SD Card
Start the boot loader, extract the binary file of the bare-metal application from the SD card to DDR, and execute it. An example command is shown below.
SOCFPGA_AGILEX # fatload mmc 0:1 0x2000000 sample_app.bin
-> Load sample_app.bin stored in FAT area of SD card to DDR address 0x2000000
SOCFPGA_AGILEX # go 0x 2000000
-> Move program counter to DDR address 0x2000000
Note:
Recent u-boots have cache enabled.
If the above command does not boot, disable the cache with the "dcache off" and "icache off" commands and try again.
3-2-4. Check the Log
If the build completes normally, the following log will be output.
U-Boot SPL 2022.01 (Sep 08 2022 - 22:48:40 +0900)
Reset state: Cold
MPU 1200000 kHz
L4 Main 400000 kHz
L4 sys free 100000 kHz
L4 MP 200000 kHz
L4 SP 100000 kHz
SDMMC 50000 kHz
DDR: 8192 MiB
SDRAM-ECC: Initialized success with 1728 ms
QSPI: Reference clock at 400000 kHz
WDT: Started watchdog@ffd00200 with servicing (10s timeout)
Trying to boot from MMC1
## Checking hash(es) for config board-0 ... OK
## Checking hash(es) for Image atf ... crc32+ OK
## Checking hash(es) for Image uboot ... crc32+ OK
## Checking hash(es) for Image fdt-0 ... crc32+ OK
NOTICE: BL31: v2.6.1(release):
NOTICE: BL31: Built : 00:44:55, Jul 28 2022
NOTICE: BL31 CLK freq = 400 MHz
U-Boot 2022.01 (Jul 28 2022 - 00:46:38 + 0900)socfpga_agilex
CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex SoCDK
DRAM: 8 GiB
WDT: Started watchdog@ffd00200 with servicing (10s timeout)
MMC: dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... In: serial0@ffc02000
Out: serial0@ffc02000
Err: serial0@ffc02000
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 8a:b9:da:d7:65 :e8
eth0: ethernet@ff800000
Hit any key to stop autoboot: 0
SOCFPGA_AGILEX #
SOCFPGA_AGILEX #
SOCFPGA_AGILEX # fatload mmc 0:1 0x2000000 sample_app. bin <- (extract app from SD card to DDR)
4856 bytes read in 5 ms (948.2 KiB/s)
SOCFPGA_AGILEX # go 0x2000000 <- (Go to the address of the application)
## Starting application at 0x02000000 . .
Hello World! <- (The result of application execution is displayed)
4. Conclusion
In this article, we have provided a bare-metal application for the Agilex™ 7 FPGA and introduced the execution procedure. Please note that the execution procedure differs between the debugger and the SD card.