During training, I was creating a 7-segment decoder in Verilog HDL,
I was creating a 7-segment decoder in Verilog HDL when I got a "latch exists" warning on Quartus II.
Here is the warning message.
Warning message
Here is the logic created at that time in RTL Viewer.
RTL Viewer
Looking at the logic in RTL Viewer, there is indeed a latch....
How did the latch get generated?
I don't remember writing anything about a latch...
Since the 7-segment decoder mainly only describes case statements, I thought that was the only possible cause, so I decided to compare the case statements with those that had worked in the past.
I found that the default statement was not included, so I added it.
The following figure shows the improved RTL Viewer with the default statement.
RTL Viewer after improvement
Yes...this is the cause!
The circuit can be changed so much by just one description of default in the case statement!
It's too delicate to handle....
By the way, the number of logic elements (LE : FPGA capacitance) consumed by the FPGA was different in the compilation report.
Number of LE consumed when a latch is generated
Number of LE consumed when a latch is not generated
Since the case statement defines the conditions and describes the expression to be executed, it is inferred that if all conditions are not covered, the previous value must be retained and the latch is configured.
If the default statement does not describe all conditions, it will generate a latch in an attempt to retain the previous value of the undescribed condition.
So it is important to remember to write the default statement.
It may be quite instructive to also look at warnings that are often overlooked.
Incidentally, I've been told a lot during my training that latches are not a good idea,
Why is latching a bad idea when it is almost the same whether you look at the symbols or the behavior?
The primitive levels look the same in the diagram above.
However, if you look at the actual latch structure, you can see that it is constructed with NAND and is fed back.
(Quartus II is amazing, I can see this much!)
) I had no idea about latches, so I asked my seniors about them!
Both latches and flip-flops are functions to hold data, but a flip-flop takes data on the rising edge (or falling edge) of the clock, and a latch holds data by repeatedly feeding back the output and returning it to the input.
The figure below shows the structure of the latch.
The delay time of the feedback varies depending on the length of the wiring, so it seems that data is not always captured at the same timing.
FPGAs and CPLDs that can be rewritten many times always contain flip-flops in their logic cells! That's what I mean.