Hello.
Since joining Altima, I have heard many different names for standards in various situations.
I would like to share with you an episode in which a big-headed Toryo deepened my understanding of the "I/O Standard," which is an important part of using Altera FPGAs, even though he had some doubts about some strange parts of it.
When I was doing technical training, the "I/O Standard" came up frequently when using Quartus® II.
It seems that different standards have different electrical characteristics, but the image is still a bit fuzzy and many questions come to mind.
First of all, as a newcomer to the world of electronics, I had some doubts about the purpose of using I/O standards before I became familiar with them.
Question 1: What is the purpose of each I/O Standard?
During the training, I had no idea what the purpose of the I/O Standard was.
However, when I looked into it, I found that the examples of I/O Standard supported by Altera FPGAs were well described in the device handbooks...
So, here is an excerpt of the general usage of each I/O Standard.
I have been choosing I/O Standards without thinking about it, but the applications are completely different.
Question 2: How are the high and low values of various input signals recognized by FPFA, and where are the reference values defined?
There are two main types of signals: single-ended and differential voltage.
For Altera FPGAs, you can download Device Datasheet and refer to I/O Standard Specifications under Operating Conditions to check the electrical specifications for each standard. (Click "Documentation" in the upper right corner of the Altera HP screen.
･Single-ended: LVTTL, LVCMOS, PCI-X, etc.
A signal is recognized by the FPGA as High if it is higher than a certain voltage value specified in the standard, and as Low if it is lower. The high and low values of input signals are based on VIH and VIL.
･Differential voltage: LVDS, BLVDS, mini-LVDS, etc.
If the potential difference between the two signals is greater than a certain value, it is recognized as High or Low.
Why is there no VID for mini-LVDS?
Scrolling down the Datasheet, I see...
Oh, so mini-LVDS is only supported on output pins in Cyclone® IV?
There are various I/O Standards, but some device series and I/O Standards have limited support, so you have to check the Datasheet carefully!
By the way, reading the Datasheet, it seems that there is an I/O Standard that uses a "reference voltage", which is a reference voltage input to the reference voltage pin and defines High/Low with respect to it.
I think I've seen VREF somewhere before...
Yes, I have seen VREF somewhere..! When I was practicing device manufacturing, I often saw this pin as a power supply pin when I referred to the Pin Connection Guidelines of the device series!
When I selected the I/O Standard in reference voltage format, I had to refer to these guidelines and supply power to the listed pins as described in the datasheet! I'm getting more and more connected!
...I was mumbling to myself, when my senior asked me one more question.
Senior "So, if I set the I/O Standard to 2.5 V on the Quartus® II and supply 3.3 V to VCCIO on the board, what will happen on the actual device?"
Toryo "Ugh... (On the actual device...? The pin information can be set in detail on Quartus II, so I should be able to follow it, but what happens if I don't follow the instructions on Quartus II...?"
Toryo was in a state of confusion, but the answer was easily found in the documents prepared by Altima.
I see, the setting on Quartus II does not determine the voltage of the device on the actual device!
In other words, if the I/O Standard is set to 2.5 V on Quartus II, but 3.3 V is supplied to VCCIO on the actual device, the voltage of the corresponding I/O bank will be “3.3 V”!
However, only one type of VCCIO can be used in one I/O bank, and in order to keep the FPGA device specification, it is better to set the pins on Quartus II, which has the characteristics of each Altera FPGA device, and check the “Pin-Out File” of the “Fitter Report” in the compilation report. File” of ‘Fitter Report’ in the compile report.
Thus, even a new engineer with such a “big head” can design “obediently to the tool” thanks to Quartus II, which is “obedient to the device”.