DDR4 Memory Operation with Altera® FPGAs! (Practical version)

Original Page: DDR4 Memory Operation with Altera® FPGAs! (Practical Guide) - Semiconductor Business - Macnica (macnica.co.jp)

The purpose of this page is to explain the process of implementing a DDR4 SDRAM memory controller on an Altera® FPGA and simulating and verifying its operation using Example Design in an easy-to-understand manner, so detailed explanations are omitted. This page is based on the Arria® 10 GX FPGA Development Kit in which Arria® 10 is implemented, but the basic flow is the same for other FPGAs that support DDR4 SDRAM controllers.

Environment

• Development Tools: Quartus® Prime Development Software v17.1 (Pro Edition or Standard Edition)
  • Pro Edition: Paid license required
  • Standard Edition: Paid license required
• Simulation Tool: ModelSim® FPGA Edition 10.5b (Quartus® Prime 17.1)
  • ModelSim® FPGA Edition: Paid license required
• Development Kit: Arria® 10 GX FPGA Development Kit　Macnica-Mouser purchase site

Quartus® Prime edition comparison ← broken link

Have you installed the tools? 
If you have not installed the tools, you can get them from the Altera® FPGA site (download).

• Download Altera® FPGA Tools
• How to install Quartus® Prime & ModelSim® FPGA Edition

Procedure

• Checking DDR4 SDRAM Interface Support Status
• Configure DDR4 SDRAM Controller IP
• Run Functional Simulation
• Compile Example Design　
• Verify operation on actual device

Checking DDR4 SDRAM Interface Support Status

The DDR4 SDRAM interface support status is described in " Implementing an External Memory Controller in an Altera® FPGA! The status of DDR4 SDRAM interface support can be checked using the External Memory Interface Spec Estimator, as described in "Implementing an External Memory Controller in an Altera® FPGA!

The external memory interface spec. estimator is used to determine the external memory interface support status. Click on the "Search and select items" button and enter the following conditions: Arria® 10 (model number: 10AX115S2F45I1SG), memory, and board specifications implemented in the Arria® 10 GX FPGA Development Kit used in this verification ←link expired.

• Family: Arria® 10 GX and GT
• Temperature range & speed grade: Industrial temperature range (I), -1
• Interface Type: Hard
• Memory Standard: DDR4
• Memory Topology & Rank: Component, UDIMM

The search results are as follows I1 in the second part of the model number indicates the temperature range & speed grade.

The results show that even for components (memory devices), the upper limit of the maximum frequency of the memory interface differs depending on the chip select of 1/2/4. Also, even for UDIMMs (Unbuffered DIMMs), the maximum frequency limits are different for single rank/dual rank.

Now, let's actually generate a controller using Quartus® Prime development software!

Configure the DDR4 SDRAM Controller IP

After launching Quartus® Prime, type Arria 10 External... in the IP Catalog search bar. ( Quartus® Prime's Standard External Memory Interfaces ). (The Standard Edition of Quartus® Prime allows you to work without a project open, while the Pro Edition requires a project to be open.)

Figure 2-1 Searching for Arria 10 External Memory Interfaces

Clicking Add opens the IP Parameter Editor, where you can enter a name and target device. In this case, do the following The target device is the device implemented in the Arria® 10 GX FPGA Development Kit.

• Entity name: ddr4
• Save in folder: C:\Worka10_ddr4_1710
• Family: Arria 10
• Device: 10AX115S2F45I1SG

Figure 2-2 Registering names and target devices

After clicking OK, the IP Parameter Editor appears. Let's make the necessary settings!

Parameters in the center is an area for making various necessary settings, and Details in the upper right corner contains links to documents and explanations of each setting item.

Figure 2-3 IP Parameter Editor

To test the Arria® 10 GX FPGA Development Kit, select the DDR4 daughter card (Arria 10 GX FPGA Development Kit with DDR4 HILO) included in the Arria® 10 GX FPGA Development Kit and click Apply. Select it and click Apply. This will automatically apply most of the memory parameter settings.

Now, in each tab of the Parameters section, we will make the necessary settings for this operation check. Other settings will be left as default. For a detailed explanation of each setting, please check Details mentioned earlier.

General tab

Confirm that Protocol is set to DDR4. This should be reflected automatically in Presets.

Next, check that the Speed Grade (FPGA speed grade) is set to I1. This should automatically reflect the controller name and target device selected earlier.

Leave the other settings at their defaults. Note that the memory interface frequency is 1066.667 MHz.

Figure 2-4 Parameters - General tab

Memory Tab

Leave as default.

Mem I/O Tab

Leave as default.

FPGA I/O Tab

Leave as default.

Mem Timing Tab

Leave as default.

Board Tab

Leave as default.

Controller Tab

Leave as default.

Diagnostics Tab

Simulation Options - Calibration mode

This setting is valid for simulation only and does not affect actual device operation.

The DDR4 SDRAM interface is not read/write ready immediately after power-on. Although a detailed explanation is omitted here, read/write and other accesses are not possible without these steps.

This calibration can be skipped in the simulation. Of course, you can check the full calibration move in simulation, but depending on the configuration, it may take a considerable amount of time.

• Skip calibration: Skip calibration
• Full calibration: Run calibration without skipping calibration

Figure 2-5 Parameters - Diagnostics tab

Example Designs Tab

Example Design Files

• Simulation
  • Check the box to simulate with Example Design.
• Synthesis
  • Check this box if you want to check the actual device with Example Design.

Generated HDL Format - Simulation HDL format

Select the HDL format for simulation.

Target Development Kit - Select board

Select the target board. However, in the Presets section above, the Arria® 10 GX FPGA Development Kit with DDR4 HILO, which is included in the Arria® 10 GX FPGA Development Kit, is used, so it should be selected.

Figure 2-6 Parameters - Example Design tab

Once configured, save this configuration by selecting File menu ⇒ Save As in the IP Parameter Editor, here named ddr4.qsys.

Next, generate an Example Design: Click Generate Example Design, specify where you want to generate the Example Design, and then click Generate. 
In this case, we specified C:\Worka10_ddr4_1710\example_design as the generation location.

Figure 2-7 Generating the Example Design

Generating the Example Design will take a few minutes. When it is successfully generated, the following window will appear, and then click Close.

Figure 2-8 Example Design Generation Completed

Since we are going to verify the operation of the Example Design, we will not generate the controller this time. If you plan to implement a controller in your FPGA design, please generate a controller.

When the Example Design is generated, a qii folder and a sim folder are created.

Figure 2-9 Folder for Example Design

Running Function Simulation

Let's run a functional simulation. The files required to run the simulation (simulation project, testbench, traffic generator, memory model, etc.) are automatically generated when the controller is generated, so the simulation can be run without any hassle.

To explain the simple operation of the simulation, addresses, commands, and data are sent to the memory controller from the traffic generator, which receives the clock supply, and are written to memory via the PHY. The data read from the memory is then compared to the data written. If the data match, Success = High; if not, Fail = High.

Figure 3-1 Simulation Project Configuration

For this simulation, we will use ModelSim® FPGA Edition.

After starting ModelSim® FPGA Edition, select File menu ⇒ Change Directory and specify the working directory. 
This time, we specify C:\Worka10_ddr4_1710\example_design\simulated_simulationmentor. Since ModelSim® is a simulator by Mentor Graphics®, we specify the mentor folder.

Figure 3-2 Change Directory

Next, in the Transcript window of ModelSim® FPGA Edition, execute the following commands in this order

1. do msim_setup.tcl (runs the script for simulation)
2. ld_debug (compile libraries/compile design files/load design)
3. add wave "ed_sim/*" (import signals into the wave window)
4. run -all (run the simulation)

Figure 3-3 Executing commands in the Transcript window

Although it depends on the PC specification, it took ModelSim® FPGA Edition about 30 minutes to complete the simulation with this configuration. (Incidentally, it took about 4 minutes with Questa® Prime/Core.)

When the simulation is finished, it stops automatically. If you want to check the waveforms after the simulation is complete, click No. (If you click Yes, the Model FPGA Edition will stop automatically. (Note that clicking Yes will close ModelSim® FPGA Edition.)

Figure 3-4 Simulation Completion

In the simulation waveform, you can see that ***_local_cal_success is set to High when the calibration is completed.

In the Example Design, write/read and compare operations are repeated, but in the simulation, the simulation is terminated after the first week. However, in the actual device verification, this continues all the way through, so it can be used for long-run testing.

Figure 3-5 Simulation Waveform (Skip Calibration)

Compilation of Example Design

Next, we prepare to compile the Example Design. The following figure shows the block diagram of Example Design.

Figure 4-1 Structure of the project for operation check

The example design generated for the Arria® 10 GX FPGA Development Kit already has various settings, constraints, and pin assignments. To be sure, let's take a look at the Pin Planner: select Assignments menu ⇒ Pin Planner in Quartus® Prime.

Figure 4-2 Pin Planner

Actually try to compile the pin planner by selecting "Start Compilation" from the "Processing" menu of Quartus® Prime.

Did the compilation finish successfully?

Figure 4-3 Compilation Completed

<Supplement> 
The timing analysis result (TimeQuest Timing Analyzer in the compilation report) is in red. This is due to the fact that timing constraints are not applied to all pins. However, since the unconstrained pins are for reset, JTAG, and LED output, we will proceed as is.

If you are experiencing timing violations in Setup or Hold, try changing the compilation settings: in Quartus® Prime's Assignments menu ⇒ Settings ⇒ Compiler Settings ⇒ Optimization mode, set Optimization mode to Performance. This setting is intended for performance-oriented compilation, which tends to improve timing, but can be resource-intensive in some cases.

5. check the operation using the development kit

After compilation is complete, write the SOF file generated by the compilation to the Arria® 10 device. Connect the development kit and PC with a USB cable (development kit side: USB Micro-B), and turn on the power.

＜ 
Altera® FPGAs are equipped with a JTAG port. Write data from this JTAG port via the FPGA download cable.

Normally, an FPGA download cable (such as USB-Blaster™ or USB-Blaster™ II ) is used, but since the Arria® 10 GX FPGA Development Kit has the Blaster function implemented on the board, a separate download cable is not required. The Arria® 10 GX FPGA Development Kit is equipped with the Blaster functionality on board, so there is no need for a separate download cable.

The included DDR4 daughter card should be mounted in the center of the development kit.

Figure 5-1 Arria® 10 GX FPGA Development Kit Cable Connections

Also check the JTAG chain settings (DIP switch/SW4 on the back).

• 1: OFF (left side)
• 2: ON (right side)
• 3: ON (right side)
• 4: ON (right side)

Figure 5-2 DIP switch settings for JTAG chain

Next, select Tools menu ⇒ Programmer in Quartus® Prime to start Quartus® Prime Programmer.

If the Programmer starts and the SOF file for writing is automatically registered, check that Hardware Setup and Mode are selected, and then click Start to execute the write operation.

If the SOF file is not registered in the Programmer, set the download cable, mode, and write file as follows, then click Start to execute the write operation.

• Hardware Setup：USB-Blaster™ II (Cannot be selected if the driver for USB-Blaster™ II is not installed) ⇒ How to install the driver for USB-Blaster™ II
• Mode：JTAG
• Add File: SOF file generated at compile time (file name: ed_synth.sof)

Figure 5-3 Quartus Prime Programmer

After the SOF file has been written, the Example Design actually runs. If it is working properly, the green LED should be lit.
Figure 5-4 Arria® 10 GX FPGA Development Kit (in operation)

The LEDs are assigned as shown in the table below. These pin assignments are also automatically assigned in the Example Design for the development kit.

Table 5-1 Pin Descriptions in Example Design (partial)

Pin Name	LED Description	Explanation
***_status_local_cal_success	D3 Green	Asserted High upon successful completion of memory initialization, training, or calibration. Indicates that the controller is ready to use the memory interface.
***_status_local_cal_fail	D3 Red	Asserted High when memory initialization (initialize), training, or calibration fails.
***_tg_0_traffic_gen_pass	D10 Green	Asserted High when the first round of write/read operation check pattern to the memory by Example Design is completed (normal). In the simulation, the pattern stops after one cycle, but in the example design for operation check, the operation check pattern is repeated.
***_tg_0_traffic_gen_fail	D10 Red	Asserted High when the first cycle of the operation check pattern for write/read to memory by the example design is completed (failed). The simulation stops after one cycle, but the operation check pattern is repeated in the example design for operation check.
***_tg_0_traffic_gen_timeout	D7 Green	Asserted High when timed out in the Traffic Genetic Timeout pattern for write/read to memory in the Example Design.

The Signal Tap logic analyzer function can also be used to monitor signals inside the FPGA. This is a topic for another time.

Recommended articles/documents are here

• Altera FPGA Development Flow / FPGA Top Page
• Implementing an External Memory Controller in an Altera® FPGA!
• DDR3 Memory Operation on Altera® FPGAs! (Practical Use) [1/2] (in Japanese)
• DDR3 Memory Operation on Altera® FPGAs! (Practical Use) [2/2] (Practical Use) [2/2] (Practical Use)
• DDR4 memory operation on Altera® FPGAs! (Practical use) [2/2] DDR4 memory operation with Altera® FPGAs!