DDR3 Memory Operation with Altera® FPGAs! (Practical version) [1/2]

This page provides an easy-to-understand flowchart for implementing a DDR3 SDRAM memory controller in an Altera® FPGA, simulating it using Example Design, and verifying its operation. This page uses the Beryll Cyclone V GX Basic Board (Beryll board) on which the Cyclone® V device is implemented, but the basic flow is the same for the Stratix® series and Arria® series, which support UniPHY-based DDR3 SDRAM controllers. The basic flow is the same for the Stratix® and Arria® series, which support UniPHY-based DDR3 SDRAM controllers.

<Agenda>.

Checking DDR3 SDRAM Support for Cyclone® V Devices
Generate DDR3 SDRAM Controller with UniPHY
Perform functional simulation
Compile Example Design
Verify operation using the Beryll board
Summary

Check the DDR3 SDRAM support status of the Cyclone® V device

The support status of DDR3 SDRAM interface is described in " Implementing an External Memory Controller in an Alteral® FPGA (Preparation)" !(Preparation) ", you can check the DDR3 SDRAM interface support status using the External Memory Interface Spec Estimator.

The external memory interface spec. estimator is used to determine the conditions. Click on the "Search Conditions and Determine Items" button and enter the following conditions, including the Cyclone® V device (model number: 5CGXFC4C6F27C7N), memory, and board specifications implemented on the Beryll Cyclone V GX Basic Board (Beryll board) used in this verification. Click on the "Search criteria and decide items" button and enter the following criteria

Family: Cyclone® V GX
Temperature range & speed grade: Commercial temperature range (C), -7
Interface Type: Soft, Hard
Memory Standard: DDR3
Memory Topology & Rank: Component, 1 Chip Select

The search results are as follows. Note that the C7 in the second half of the model number indicates the temperature range & speed grade.

From this search result, we can see that the Beryll board has

Hard memory controller (HMC): up to 400 MHz (800 Mbps)
With a soft memory controller (SMC), the maximum frequency is 303 MHz (606 Mbps)

The maximum frequency for a soft memory controller (SMC) is 303 MHz (606 Mbps). Therefore, in this case

With a hard memory controller (HMC), the memory interface frequency is 400 MHz (800 Mbps).

We will use a hard memory controller (HMC) with a memory interface frequency of 400 MHz (800 Mbps).

Let's generate the controller using Altera® Quartus® Prime development software!

<Tools to use

Quartus® Prime Development Software v16.0: Standard Edition or Lite Edition
Standard Edition: Paid license required
Lite Edition: No license required
ModelSim® - FPGA Edition 10.4d (Quartus® Prime 16.0)
ModelSim® - FPGA Edition: Paid license required
ModelSim® - FPGA Starter Edition: No license required

Have you installed the tools?
If you have not installed the tools, you can obtain them from the Altera® FPGA site (download).

2. generating DDR3 SDRAM controller with UniPHY

First, let's generate a memory controller!

Launch Quartus® Prime development software and search for DDR3 SDRAM Controller with UniPHY by typing DDR3 in the IP Catalog search bar.

A screen will appear where you can set up a directory to generate various controller-related files and a name for the controller. Also select the language (Verilog or VHDL) in which to generate the files and click OK. At this time, avoid double-byte characters and single-byte spaces in the path and file name! This time, name the controller ddr3.

The controller configuration screen will then appear. Let's make the necessary settings!

First, enable HMC.

We will make the necessary settings from here on, but this time, we will only make the minimum settings necessary to check the operation on the Beryll board. Other than that, we will leave the default settings as they are.

For details, please refer to the EMIF Handbook.

PHY Settings tab

In this case, a 50 MHz clock is used as the reference clock.

Speed Grade: 7
Memory clock frequency: 400.0 MHz
PLL reference clock frequency: 50.0 MHz
Rate on Avalon-MM interface: Full
Article header beryll ddr3 fig3 4 1

Memory Parameters tab

The Beryll board has two Micron MT41J64M16 DDR3 SDRAMs. Each of these memories is 16 bits wide, so the total width is 32 bits.

Click "Preset for ..." on the right side of the screen to find out which memory is implemented. on the right side to find the implemented memory. Here, typical memories are listed in advance, with detailed parameters already set. Luckily, in this case, there is a memory that is implemented, so select it and click Apply. The memory configuration and parameters are then reflected. If the memory you want to use is not in the list, select a memory with a similar configuration, edit the parameters while looking at the datasheet, give it a name, and save it for easy recall the next time.

Since the data between the Cyclone V device and the memory on the Beryll board is connected at 32-bit width, we will use 32-bit width for this verification.

This time, only the following settings are to be made in the Memory Parameters tab.

Total interface width: 32

Memory Timing tab

Since the memory information was reflected in the Memory Parameters tab earlier, leave the settings as they are.

Board Settings tab

This time, leave the default settings as they are.

Controller Settings tab

Leave as default for this time.

Diagnostics tab

This time, only the Auto-calibration mode is set. This setting is valid only for simulation and does not affect actual device operation.

The DDR3 SDRAM interface is not read/write ready immediately after power-on, but initialization and calibration are performed first. Although a detailed explanation is omitted here, read/write and other accesses are not possible without these steps.

This calibration can be skipped in the simulation. Of course, you can also check the full calibration move in simulation, but depending on the configuration, it may take a considerable amount of time, so be prepared for it. Auto-calibration mode sets the degree to which this calibration is skipped.

Skip calibration: Skip calibration
Quick calibration: Perform calibration only partially
Full calibration: Perform calibration without skipping calibration

Generate Controller

Click "Finish" to generate the controller. At this time, check the Generate Example Design checkbox and click Generate to simultaneously generate an environment (Example Design) for easy simulation and actual device operation, as shown in the figure below.

Generating the controller will take about several minutes. When generation is complete, click Exit.

Continue to " DDR3 Operation with Altera® FPGAs! (Practical Use) [2/2] ".