Hello, my name is Bee.
Previously, have studied the time it takes to enter user mode, but it was not clear what is the difference between Power On Reset ( POR ) and initialization.
We will study the difference again, this time using the Cyclone® IV E as an example.
I had always thought that "reset" meant setting the FPGA internals to "0" and that "initialization" meant initializing the FPGA.
And I have heard that in Altera's FPGAs, initialization is to assign "0" to a flip-flop.
I had an impression that POR is the start period after power-on, and initialization is the preparation period before entering user mode.
Power On Reset
The POR circuit keeps the entire device in a reset state until the respective supply voltage levels stabilize.
The following three power supplies are monitored.
● VCCINT
● VCCA
● VCCIO * Only I/O Banks with configuration and JTAG pins are monitored.
Note: Different device families have different supply voltages monitored by POR.
That is, when the power supplies of the above three power supplies (VCCIN, VCCA, and VCCIO (*)) meet the power supply specifications, the POR circuitry releases the reset and the configuration is initiated.
During the POR period after power-on, the device is in a reset state, as shown in the table below.
When each supply voltage reaches the specified value, POR ends and configuration starts by releasing the nSTATUS.
If you wish to start configuration after a certain amount of time has elapsed after the power supply has stabilized (after POR has ended), you can manually set nCONFIG to Low and then set nCONFIG to High at the timing when you wish to start configuration.
We received the following question from a customer.
Customer: "There is a device on the board that starts running faster than the FPGA after power-on. Since it is wired to the FPGA on the board, could you please tell me the status of the FPGA pins?"
It is true that I did not know the status of each pin of the FPGA before the configuration.
If the configuration is not finished, each pin will be in a state where it is not decided whether it is an input pin or an output pin.
I thought that ”all pins will be in the same state... During configuration, the configuration pins are transmitting configuration data...”.
I checked the Cyclone® IV handbook for the I/O status in each phase and found the following description.
(Click here for the description in the handbook => Configuration -> Configuration -> Reset )
The I/O pins are tri-stated until the device enters user mode.
The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are always enabled (after POR) before and during configuration. pull-up resistors are not enabled prior to POR.
The user I/O and dual-purpose I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are always enabled (after POR) before and during configuration.
The resistance value of the Pull-Up resistor for the I/O present inside the device is listed in the datasheet and depends on the voltage level of VCCIO.
( Operating Condition -> DC Characteristics -> Internal Weak Pull-Up and Weak Pull-Down Resistor )
Cyclone® IV Internal Weak Pull-Up and Weak Pull-Down Resistor
It appears that the POR is not working properly due to the power supply swing, resulting in a configuration failure.
If the configuration fails, we are likely to analyze only the part related to the configuration, but we will not forget to check the voltage at power-on as well.
Initialization
Next, what kind of initialization is done during initialize?
As the name suggests, the initial state of the device is set according to the state of the logic so that the designed logic can start operating.
The following primitives inside the device are set to the initial state of the design.
● LUT (look-up table)
● Registers
● I/O
● Memory block
● Multiplier block
Summary
We now understand the difference between POR and initialization.
● POR: At power-on, the entire device is reset until the supply voltage reaches the specified value.
● Initialize: Initial values are set in registers, memory, etc. inside the FPGA.
As you asked, there should be no FPGA alone on the board... So, we could check the status of user I/O and dual-use pins when the FPGA is not in user mode, but how can the configuration pins behave as configuration pins and when can the configuration mode be changed? When is the configuration mode known?
We will investigate the configuration sequence in the next issue.
These were the differences between POR and initialization! Configuration is one word, but it is very deep....
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