Solve Intel® FPGA Functional Simulation with NativeLink

Hello.

My name is Intel F. Hanako and I am a technical support engineer for Intel® FPGA products at Macnica.

I assume you are using an EDA simulator to functionally simulate your design for Intel FPGAs. In this article, I would like to introduce "NativeLink Simulation" as part of the workflow. This is a flow that Hanako also recommends!

This time, we will use Questa* - Intel® FPGA Edition (hereinafter referred to as Questa- IFE, including Starter Edition) as a simulation tool.

What is NativeLink?

Running EDA tools from Quartus® Prime is called NativeLink.

For example, a click on the Quartus Prime menu will automatically <Questa - IFE starts, compiles and loads the simulation, displays the simulation results in the waveform window>, and so on.

This flow is highly recommended not only for those who do not know how to operate Questa - IFE GUI, but also for those who want to improve operational efficiency.

Hanako's Tweet

If your design includes IP (Intellectual Property) modules created with IP Catalog or Platform Designer, do you know which simulation library to use for your simulation tool?

NativeLink Simulation can help you to eliminate such concerns!

This way, all the simulation libraries needed to functionally simulate IP modules are automatically loaded for you.

Supported Environments for NativeLink

The environments in which NativeLink can be used are listed below.

Table 1. NativeLink Supported Environments (Note 1)
Supported Quartus Prime	Quartus Prime Standard Edition / Quartus Prime Lite Edition * Pro Edition is not supported (Please refer to this content for Pro Edition)
Supported simulation and tools (Note 2)	Aldec Active-HDL / Riviera-PRO Cadence Xcelium* Parallel Logic Simulation Siemens EDA ModelSim SE / Questa Advanced Simulator Siemens EDA Questa -Intel FPGA Edition Synopsys VCS / VCS MX

Note 1: All Schematic designs (.bdf) must be converted to HDL.

Note 2: Please check the release notes for the version of Quartus Prime you are using for the supported versions of each EDA tool.

Setting up the environment

Set up an environment to run NativeLink.

1. Click EDA Tool Options under Tools -> Options -> General in Quartus Prime.
2. Click the[...] button on the right end of the Questa - Intel FPGA line and specify the absolute path of the folder where the executable program is saved.
If you are using Windows OS, specify the win64 folder where questasim.exe is saved.

EDA Tool Options

Work Flow

1. register all the designs required to compile Quartus Prime in the Quartus Prime project.

Select "Project" menu -> Add/Remove Files in Project

* If your design includes IP, be sure to check Hanako's Point 1) and 2).

* If your design does not include IP, please go to 2.

Hanako's Point 1)

If your design includes IPs created by Platform Designer

Enable the "Create simulation model option" in the Generation dialog box that pops up when Generate HDL is executed.
Clicking the Generate (or Generate HDL) button after selecting the language to generate will also generate a function model for the simulation tool.

Generation Dialog Box

Hanako's Point 2)

If your design contains "IP modules created in Platform Designer" or "IP modules selected from the IP Catalog and created based on Platform Designer's GUI," you can use Quartus Prime's <ip_ name>.qip as well as <ip_name>.sip using the following menu in Quartus Prime.

Project menu -> Add/Remove Files in Project

* IP modules created by selecting an IP from the IP Catalog and using the MegaWizard Plug-In Manager based GUI" will not generate *.sip files.

　Only *.qip files should be registered with the project.

Registering sip files to the Quartus Prime project

The location of the .sip file depends on whether you created the IP module in IP Catalog or Platform Designer.

[IP modules created in IP Catalog]

A .sip file is generated in the folder where <ip_name>.v (or .vhd) was created.
(* This is in the same hierarchical folder as the <ip_name>_sim folder.)

Folder structure of IP modules created by IP Catalog

[ IP modules created by Platform Designer ]
<ip_name>. .sip files are generated in the folder -> simulation folder.

Folder structure of IP module created by Platform Designer

2. Select Assignments -> Settings -> EDA Tool Settings -> Simulation and set the following items in the EDA Netlist Writer settings.

Tool name : Questa Intel FPGA (* Select this option for Starter Edition)
Format for output netlist : Verilog HDL (Reference: Hanako's Point 3))
Output directory : simulation/modelsim (default is recommended)

EDA Netlist Writer settings

Hanako's point 3)

Even if your simulation model or testbench is VHDL when you create IP, we recommend you to select Verilog HDL for this option.
This language selection affects the vsim -L command in the NativeLink runtime script.
In recent IP, even if the language choice for the simulation model is VHDL, the underlying model is often configured in SystemVeriog, which inevitably requires a simulation library for Verilog HDL. In this case, it is necessary to specify the library for Verilog HDL by using the vsim -L command, so please use Verilog HDL for the Format for output netlist even if the model is generated in VHDL.

3. Register a test bench in NativeLink settings.

Select "Compile test bench" and click "Test Benches" button.

NativeLink settings

Click the New button in the Test Benches window.

Test Benches window

In the New Test Benches Settings dialog box, set the following items.

Test bench name : Enter the module name of the test bench (also enter the Top Level module in test bench field in the lower row).
Simulation period : Set the end time of simulation execution.
File name : Click the [...] button on the far right. Click the [...] button on the far right to select a test bench file and click the Add button to register it.

New Test Benches Settings dialog box

Close each window with "OK" and return to the Settings window.

4. Execute a function simulation with NativeLink!

　　Click Tools menu -> Run Simulation Tool -> RTL Simulation.

*To run RTL Simulation, Analysis & Elaboration, Analysis & Synthesis, or Fitter process must be executed beforehand.

However, do not run Start Compilation (Processing menu), as it will automatically run EDA Netlist Writer and will not generate a valid script for RTL Simulation.

(If you have run a full compilation, run Analysis & Elaboration or Analysis & Synthesis or Fitter again before running RTL Simulation).

RTL Simulation

Questa - IFE compiles, applies and loads libraries, adds signals to the Wave window, and runs the simulation. All these operations are performed automatically and the waveforms are displayed in the Wave window.

Simulation Run

All the user has to do is check the Wave Window! How efficient!

We hope you will try to use NativeLink for your function simulation.