Recent Altera® FPGAs support external memory interfaces (External Memory Interface / EMIF) such as DDRx as a matter of course. By the way, EMIF is referred to as "eMIF" in the Altera® FPGA community.
When you think of implementing a memory controller in an Altera® FPGA, what do you think about first?
- Which FPGA devices support it?
- What memory standards are supported?
- What transfer rates are supported?
And so on.
This page introduces the process from selection to operation verification, using DDRx SDRAM controllers as an example, for those who are implementing EMIF with Altera® FPGAs for the first time.
Checking EMIF Support Status
Here is a useful page for checking the EMIF support status of Altera® FPGAs.
The External Memory Interfaces Spec Estimator on this page allows you to check the EMIF support status of Altera® FPGAs. You can search by device family, speed grade, interface type, memory standard, frequency, and more.
Clicking on "Set Search Criteria and Items" will bring up the following settings screen.
At first, you should not set up too many guts, but specify a roughly understandable range, and then gradually add more criteria to narrow down the search.
Family
Check the device families that you want to use or are candidates to use. Multiple device families can be checked.
If you do not check any family at all, all device families will be targeted.
Temperature Range & Speed Grade
Check the temperature range and speed grade of the device.
＜Temperature Range >
The following temperature ranges exist. However, some devices have a temperature range while others do not. Please refer to the documentation of each device for details.
- Commercial temperature range (C product): Junction temperature 0 to 85°C
- Industrial temperature range (I): Junction temperature -40 to 100°C
- Automotive temperature range (Part A): Junction temperature -40 to 125°C
- Extended temperature range (E): Junction temperature 0 to 100°C
- Military temperature range (M): Junction temperature -55 to 125°C
<Speed Grades>
Each device family has a certain number of speed grades. Please refer to each device's documentation for details.
Interface Type
- Software
- Consumes FPGA resources such as logic and internal memory to implement a memory controller. Often referred to as a soft memory controller (SMC).
- Hard
- Uses a memory controller that is pre-installed as a hard macro inside the device. Often referred to as a hard memory controller (HMC).
- Hard HPS
- Uses the memory controller in the hard processor system (HPS) of an SoC FPGA with an embedded ARM* core.
Memory Standard
Select the external memory standard.
Local interface clock rate
Select the clock rate for the local interface, if specified in advance.
The image below illustrates the clock rate. (For simplicity, a double data rate of 400 MHz (800 Mbps) is used between the controller and memory.)
Simply put, data is transmitted between the controller and memory at a high speed and double data rate, but the data in the FPGA cannot be processed at the double data rate, so it is first converted to a single data rate at the same frequency. But at this time, the data width is doubled. This is the full rate.
Next, if the frequency is too high for data processing in the FPGA at the full rate, the frequency is further halved. But at this time, the data width is further doubled. This is the half rate.
If the frequency is too high for data processing in the FPGA even at the half rate, the frequency is further halved. But in this case, the data width is further doubled. This is the quarter rate.
Memory Topology & Rank
This item first selects the memory topology. For DIMMs, you must also select the type of DIMM.
For DIMMs, select the rank of the DIMM.
For components, specify the number of chip selects.
Interface I/O Location
This item specifies in which bank of the FPGA the EMIF-related pins are located; some FPGAs support different transfer rates depending on the location of the I/O bank.
I/O Standard
Select the I/O standard (I/O Standard) for the memory interface.
Maximum Frequency (MHz)
Specify the upper and lower frequency limits of the memory interface (between memory controller and memory).
Search Results
Click "Search" to display results that meet the specified conditions. After the results are displayed, you can further specify conditions to narrow down the search.
From these results, you have found a candidate FPGA to adopt for the external memory interface part. Please consider the FPGA to use, taking into account other interfaces, conditions, and specifications.
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Practical Application
This section introduces how to generate and simulate the memory controller to be implemented in an Altera® FPGA and how to check its operation using the development kit.
DDR4
DDR4 memory operation in Altera® FPGAs! (Practical version)
DDR3
DDR3 Memory Operation with Altera® FPGAs! (Practical) [1/2]
Design and Debug Guidelines
As the external memory interface (External Memory Interface/EMIF) speeds up, the data valid window shrinks and signal quality deteriorates.
Since the time spent on verification and debugging to meet the required specifications is on the rise, it is important to design device boards according to appropriate procedures and to implement means for debugging in advance during the design phase.
This document shows the design flow and debug flow, and is intended to help designers avoid defects by following the proper procedures and to solve problems quickly by implementing the necessary mechanisms for debugging.
Click here for recommended articles/documents
- Altera FPGA Development Flow / FPGA Home Page
- Implementing an External Memory Controller in an Altera® FPGA!
- DDR3 Memory Operation in Altera® FPGAs! (Practical Application) [1/2]
- DDR3 Memory Operation on Altera® FPGAs! (Practical Use) [2/2] (Practical Use) [2/2] (Practical Use)
- DDR4 memory operation on Altera® FPGAs! (Practical use) [2/2] DDR4 memory operation with Altera® FPGAs!