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DDR3 Memory Operation with Altera® FPGAs! (Practical version) [2/2]

DDR3 Memory Operation with Altera® FPGAs! (Practical version) [2/2]

  • Updated

Continued from " DDR3 Operation with Altera® FPGAs! (Practical Use) [1/2] ". 3.

 

Running Functional Simulation

Next, we will run a functional simulation. The files required to run the simulation (simulation project, testbench, traffic generator, memory model, etc.) are automatically generated when the controller is generated, so you can simulate without any hassle.


To illustrate the simple operation of the simulation, addresses, commands, and data are sent to the memory controller from the traffic generator, which receives the clock supply, and are written to memory via UniPHY. The data read from memory is then compared to the data written. If the data match, Success = High; if not, Fail = High.

First, let's look at the directories and files after the controller is created!

 

As shown in the figure above, the Quartus® Prime project for simulation has been generated. (You can also drag & drop the QPF file from Windows Explorer onto Quartus® Prime.)

Once the project is open, select Tools menu ⇒ Tcl Scripts in Quartus® Prime, select the simulation configuration TCL file, and click Run to execute it. At this point, select the HDL (Verilog or VHDL) that you chose when generating the controller. When the TCL file is finished running, click Close.

 

Next, launch ModelSim® - Altera® FPGA Edition. Once launched, select ModelSim® - Altera® FPGA Edition's File menu ⇒ Change Directory and choose Example Design Storage Directory ⇒ simulation ⇒ verilog or vhdl ⇒ mentor.

 

In the directory you have moved to, a DO file for running the simulation has been created. Type do run.do in the Transcript window of ModelSim® - Altera® FPGA Edition and press Enter to run the simulation.

 

It will take a few minutes for the simulation to complete. When the simulation is finished, it will stop automatically.

Click No if you want to check the waveforms after the simulation is complete. (Note that clicking Yes will close ModelSim® - Altera® FPGA Edition.)


Compile the Example Design

Next, let's compile the design for the Cyclone® V device on the Beryll board. To compile, you will need various settings, constraints, and pin assignments.

 

If you have already purchased a Beryll board, you can download the schematic and user's guide from the dedicated Mpression page. You can assign pins while viewing these, but for those who are reading this page, we have prepared a TCL file that will allow you to easily assign pins in the DDR3 Example Design. After downloading this TCL file, save it in the Example Design project directory. You can also download a special schematic of the Beryll board from this page.

Next, open the project of the example design for the operation check by selecting the project for the operation check (QPF file) from the File menu ⇒ Open Project on Quartus® Prime. (You can also drag and drop the QPF file from Windows Explorer onto Quartus® Prime.)

 

Once the project is open, change the device to the Cyclone® V device model number 5CGXFC4C6F27C7N, as the Beryll board has that model number. The N at the end of the part number indicates that the device is lead-free; Quartus® Prime does not display this N, so choose 5CGXFC4C6F27C7.

After opening the project for operation check, select Processing menu ⇒ Start ⇒ Start Analysis & Synthesis to execute the logic synthesis. (When the synthesis is successfully completed, Analysis & Synthesis in the Tasks window will change to a green check mark.

 

Select Tools menu ⇒ Tcl Scripts, select the TCL file (①), and click Run. This is the TCL file that was generated at the same time as the controller was created and allows you to set the I/O standards and other constraints for the pins related to the DDR3 interface.

Next, execute the TCL file ②. This is the pin assignment TCL file for the Beryll board mentioned earlier and can be downloaded from within this article. If you do not see it, please check again where you saved the file.

 

Run Pin Planner from Quartus® Prime's Assignments menu ⇒ Pin Planner, and check that the pin assignments and pin constraints are correct.

 

Once you have completed this step, compile the device by selecting "Processing" menu ⇒ "Start Compilation" in Quartus® Prime.

Did the compilation finish normally?

 

<Supplement 1> 
The timing analysis result (TimeQuest Timing Analyzer in the compilation report) is in red. This is due to the fact that timing constraints are not applied to all pins. However, since the unconstrained pins are for reset, JTAG, and LED output, we will proceed as is. 
If you are experiencing timing violations in Setup or Hold, try changing the compilation settings: in Quartus® Prime's Assignments menu ⇒ Settings ⇒ Compiler Settings ⇒ Optimization mode, set Optimization mode to Performance. Since this setting is aimed at performance-oriented compilation, it tends to improve timing, but may consume more resources in some cases.

<Supplement 2> 
If you want to change the memory controller settings, open ddr3.v, change the settings, and regenerate it. At this time, pin information will be lost, so it is recommended to export pin information before making changes.
FAQ] Is there a way to export pin information from an existing project and import it into another project?


5. check the operation using the Beryll board

After compilation is complete, write the SOF file generated by the compilation to the Cyclone® V device. connect the Beryll board and PC with a USB cable (Beryll side: USB Mini-B) and turn on the power.

<Supplementation> 
Altera® FPGAs have a JTAG port. Write data from this JTAG port via the Altera® FPGA download cable.

Normally, an Altera® FPGA download cable (such as USB-Blaster™ or USB-Blaster™ II ) is used, but since the Beryll board has the Blaster function implemented on the board, a separate download cable is not required. The Beryll board has the Blaster functionality implemented on the board, so there is no need for a separate download cable.

 

Next, select Tools menu ⇒ Programmer in Quartus® Prime to start Quartus® Prime Programmer.

Once the Programmer starts and the SOF file for writing is automatically registered, make sure that Hardware Setup and Mode are selected, then click Start to start writing.

If the Programmer starts up fresh, set the download cable, mode, and write file as follows, then click Start to execute the write.

  • Hardware Setup: Select USB-Blaster™ (you must have the USB-Blaster™ driver installed to select this option)
  • Mode: Select JTAG
  • Add File: Select the SOF file generated during compilation (file name: <controller name>_example.sof)

 

After the SOF file has been written, Example Design is actually running. If it is working properly, LED2 and LED5 should be lit.

 

The pin assignments in the TCL file are as shown in the table below. The LEDs are assigned as shown in the table below. When a pin is at a low level, the LED is lit.

Looking at this LED alone, you may not be able to tell if the device is really working or not. In such a case, it might be interesting to incorporate logic such as blinking the LED while it is moving.

You can also use the SignalTap® II logic analyzer function to monitor the signals inside the FPGA. This is a topic for another time.


Table 6-1 Pin Descriptions in Example Design (partial)

Pin Name
LED
Description
local_Init_done
LED0
Asserted High when memory initialization (initialize), training, or calibration is complete.
local_cal_success
LED1
Asserted High upon successful completion of memory initialization (initialization), training, or calibration. Indicates that the controller is ready to use the memory interface.
local_cal_fail
LED2
Asserted High when memory initialization (initialize), training, or calibration fails. local_init_done is not asserted at this time.
drv_status_test_complete
LED3
Asserted High when the first cycle of the write/read memory test pattern by Example Design is complete. The simulation stops after one cycle, but the operation check pattern is repeated in the Example Design for operation check.
drv_status_pass
LED4
Asserted High when the first round of write/read operation check patterns to memory by the Example Design is successfully completed.
drv_status_fail
LED5
Asserted High when a write/read operation check pattern to memory by the Example Design fails.

 


6. summary

We hope that the following agenda has given you an idea of what we have covered so far.

  • Check the DDR3 SDRAM support status of the Cyclone® V device
  • Generate DDR3 SDRAM controller with UniPHY
  • Running Functional Simulations
  • Compile an Example Design
  • Verify operation using the Beryll board

The basic flow is the same for the Stratix® and Arria® series, which support UniPHY-based DDR3 SDRAM controllers.

We encourage you to try this procedure.

When actually incorporating the controller into a user design, the Traffic Generator part of the Example Design is replaced with the user logic as shown in the figure below. The user logic and the controller are connected via the Avalon-Memory Mapped (Avalon-MM) interface.

 

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