Hello, my name is Masuo.
I asked my senpai how to determine whether the 0V of an I/O pin is due to GND or open when it shows 0V, and he told me that the current-voltage characteristics of semiconductors are measured with a curve tracer.
Figure 1: Curve tracer measurement system
I-V curve measurement between power supply pins (VCCINT, VCCIO) and GND
The I-V curve between the FPGA core power supply (VCCINT), I/O power supply (VCCIO), and GND was measured (Figure 2).
The maximum current value was set to 10mA, and the current flowing when the voltage was scanned from -3.3 to +3.3V was measured.
Figure 2: I-V curve measurement (power supply vs. GND)
These are the measurement results comparing a good FPGA and a mass-man FPGA.
Figure 3a: Good FPGA
Figure 3b: Mass-man FPGA
Figure 3a and Figure 3b are equal, and the I-V characteristics of the power supply and GND in Mass Production's FPGA were normal.
I-V curve measurement between I/O pins and GND
The I-V curve between the I/O pin (pin number 72) and GND was measured (Figure 4).
The maximum current value was set to 10mA, and the current flowing when the voltage was scanned from -3.3 to +3.3V was measured.
Figure 4: I-V curve measurement (I/O pins vs. GND)
These are the measurement results comparing a good FPGA and a mass-manufactured FPGA.
Figure 5a: Good FPGA
Figure 5b: Mass-man FPGA
The I/O pin (pin no. 72) of Mass Man's FPGA did not draw any current no matter how much voltage was applied to it, showing an open characteristic.
Looking at the contents of the FPGA package!
Figure 6 shows the contents of the FPGA package.
There is a silicon die in the center of the package, and the silicon die and I/O pins (Lead Frame) are connected by bonding wires (Gold Wires).
Figure 6: Diagram of FPGA Package Contents
Figure 3b shows that the silicon die is not damaged, and Figure 5b shows that the bonding wire of the I/O pin (pin number 72) is probably broken.
Therefore, it can be predicted that the LED did not light up because of 0 V due to an open rather than a low output.
Figure 7: Possible FPGA breakage due to bonding wire breakage
Masuo has an idea of how this happened.
→ See Masuo's FPGA Board Fabrication 1, "Absolute Maximum Voltage Ratings".
I predict that the bonding wire may have melted and disconnected because a voltage higher than the maximum rating was applied to the FPGA.
I was able to get the LED to light up by changing the I/O pin number that is wired to the LED!
What I learned
- Applying a voltage higher than the absolute maximum rating to the FPGA may have melted the bonding wire and caused the disconnection between the silicon die and the IO pin.
- If you want to check the current-voltage characteristics (open or short) of the FPGA, use a curve tracer to measure the current-voltage characteristics.
"Masuo Red Board" is completed.
Overcoming various troubles, we were able to complete the FPGA board with clock function.
The production period was about one month.
The name of the board is "Masuo Blush Board."
Masuo Blush Board
Masuo's FPGA Board Design Series (6 episodes in total) is a column that describes the process of solving various troubles that a new employee encountered when he designed his first FPGA board.
This series is a compilation of know-how and advice given by veteran senior employees, and is sure to be full of useful information for readers!
We would like to take this opportunity to thank our senior employees for their guidance.
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