This is an updated version of the former title "Techniques for using DS-5 - Register View [3/3] FPGA Side Register Display".
Arm® DS-5 for Intel® SoC FPGA Edition (DS-5) has been replaced by Arm® Development Studio for Intel® SoC FPGA Edition ( Arm® DS is the successor to DS-5 and is not significantly different in usability. Most of the articles in this series are applicable to both Arm® DS and DS-5, but the differences are clearly noted in this update.
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This article provides additional information on how to use Arm® DS / DS-5, which is available as a software integrated development environment for Intel® SoC FPGAs.
Arm® DS / DS-5 for Intel® SoC FPGAs is a product called "Intel® SoC FPGA Edition". The only difference between the Intel® SoC FPGA Edition and the Arm® official edition is the supported devices to be connected, and there is no difference in the usage of the debugger and attached tools (compiler/linker, etc.) themselves. Therefore, it is basically possible to understand how to use Arm® DS / DS-5 by referring to the Arm® DS / DS-5 manuals published by Arm®.
Arm® Development Studio documentation page (Arm® Developer site)
DS-5 documentation page (Arm® Developer site)
This article describes how to display FPGA-side registers in the register view of Arm® DS / DS-5.
Automatic Generation of Register Definition Files
When you create a hardware design for an SoC FPGA using Platform Designer (formerly Qsys ), a register definition file (.svd) is automatically generated.
Auto generated location
[Quartus Project Directory]/soc_system/synthesis/soc_system_hps_0_hps.svd
By loading the above register definition file into Arm® DS / DS-5 in the same way as described in the previous article, the registers on the FPGA side can be displayed in the register view. (Select "Add peripheral description file from directory" in Debug Configuration)
The following is an image of the Register View with the FPGA-side registers displayed.
Note that if you load both the automatically generated register definitions and the sample register definitions (.tcf) from the previous article, you will see a number of warning messages starting with "Warning (TAD231):xxxx ", but all of these messages can be It is safe to ignore them.
These messages are displayed when the names of the peripherals used in the register definition file are duplicated. In the sample register definition (.tcf), additional register definitions are written for the peripherals defined from the beginning (dmanonsecure, dmasecure, mpul2, mpuscu), but the automatically generated register definition (.svd) also contains peripherals are described, so the behavior seems to warn of duplication when both register definitions are read.
IP Components Supporting Register Display
Automatic generation of register definitions is limited to IP components that are Platform Designer (formerly Qsys ) compliant and support register definition files (CMSIS-SVD).
The CMSIS-SVD support for IP components is somewhat described in the Intel® Quartus® Prime Software User Guide - Platform Designer document, but it is not sufficient, so it is better to refer to existing IP components. It is better to refer to the existing IP components.
See: Intel® Quartus® Prime Standard Edition User Guide - Platform Designer
See: Intel® Quartus® Prime Pro Edition User Guide - Platform Designer
For reference, we checked the files of IP components (PIO) that support CMSIS-SVD and found that CMSIS_SVD_FILE is set as Interface Property in the _hw.tcl file.
The description in the blue box in the image below is the relevant description.
If you want to create an IP component that supports CMSIS-SVD, the following measures are required.
* Prepare register definition files in .svd format.
* Write a description in _hw.tcl that specifies CMSIS_SVD_FILE in set_interface_property.
Please also refer to the documentation page linked below, as more detailed information can be found at
on a community site (Rocketboards.org) that distributes Intel® SoCFPGA related information.
See also: Using CMSIS with Custom FPGA Logic
Referencing registers that do not support register views
It is also worth mentioning how to reference desired registers without adding register definitions. In addition to the register view, the following windows can be used to reference registers.
* Expression view
* Memory view
Below is an image showing how to reference registers in each view.
We have described how to customize the register view, but if register definitions are troublesome, you can use the method shown in the image above to reference registers.
This article is the last in a three-part series on how to use the register view in Arm® DS / DS-5.
Recommended articles and documents
Techniques for using Arm DS - Register View [1/3] Basic Settings
Techniques for using Arm DS - Register View [2/3] Register Definitions by Yourself
Techniques for using Arm DS - Register View [3/3] FPGA Side Register Display