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Techniques for using Arm DS - Register View [2/3] Register Definitions by Yourself

Techniques for using Arm DS - Register View [2/3] Register Definitions by Yourself

  • Updated

*This is an updated version of the former title "Techniques for using DS-5 - Register View [2/3] Register Definitions by Yourself".

Arm® DS-5 for Intel® SoC FPGA Edition (DS-5), the standard software integrated development environment for Intel® SoC FPGAs, has been replaced by Arm® Development Studio for Intel® SoC FPGA Edition ( Arm® DS is the successor to DS-5 and is not significantly different in usability. Most of the articles in this series are applicable to both Arm® DS and DS-5, but the differences are clearly noted in this update.

 

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Introduction

This article provides additional information on how to use Arm® DS / DS-5, which is available as an integrated software development environment for SoC FPGAs.

Arm® DS / DS-5 for SoC FPGAs is a product called "Intel® SoC FPGA Edition". The only difference between the Intel® SoC FPGA Edition and the Arm® Standard Edition is the supported target devices, and there is no difference in the usage of the debugger and attached tools (compiler/linker, etc.). Therefore, it is basically possible to understand how to use Arm® DS and DS-5 by referring to the manuals published by Arm®.

____.png Reference information: Arm® Development Studio document page ( Arm® Developer site)

____.png Reference information: DS-5 documentation page ( Arm® Developer site)


This article describes how to add new display items (register definitions) to the register view in Arm® DS / DS-5.

 

1. Peripherals that do not support the register view

The register view of Arm® DS / DS-5 has already defined registers for the various peripherals listed in the HPS Technical Reference Manual. The register view can be displayed by simply selecting the display items described in the previous article.

However, for peripherals implemented using Arm® IP, some of the registers are not defined in detail, so the values cannot be set/checked using the register view.

The following peripherals are not supported in register view

  • DMA Controller (DMA-330)
  • L2Cache Controller (L2C-310)
  • Cortex®-A9 MPCore Built-in SCU (Snoop Control Unit)
  • Interrupt Controller (GIC: PL-390) with built-in Cortex®-A9 MPCore
  • Timer (GlobalTimer, PrivateTimer, WatchdogTimer) with built-in Cortex®-A9 MPCore

For peripherals that do not support register view display, detailed register specifications are not described on the register map either, but the base address and links to documents that should be referenced are provided.

____.png Reference information: Cyclone® V SoC HPS Address Map and Register Definitions

 

2. How to add a register definition

By writing register definitions in .svd or .tcf format (both XML-based file formats), you can freely define registers that correspond to the register view display.

The register definitions that are initially displayed are also stored under the Arm® DS / DS-5 installation directory and can be used as a reference when writing the .tcf file (definitions for other devices are also stored in nearby directories).

<Arm® DS / DS-5 Install Directory>/sw/debugger/configdb/SoCs/altera/hps_svd.tcf

For .svd reference, files in .svd format are stored under the Quartus® Prime development software installation directory.

<Quartus® Prime Install Directory>/ip/altera/hps/altera_hps/altera_hps.svd

The register definition file is stored in the directory containing the .tcf or .svd file with "Add peripheral description file from directory" selected on the File tab of the debugger connection settings (Debug Configuration) of the Arm® DS / DS-5. will cause the register definition to be loaded when connecting to the debugger. No other special configuration is required.

The following is an image of the configuration screen for specifying the register definition file.

Figure 1. Specifying the register definition file

 

3. Difference between .svd and .tcf

The format of the register definition file can be either .tcf or .svd.

For .svd, it is standardized as System View Description (SVD) in the Cortex Microcontroller Software Interface Standard (CMSIS) The XML format is also available in the CMSIS
SoC FPGA Embedded Development Suite (SoC EDS) User Guide also describes only how to use .svd, so .svd seems to be the recommended format (.tcf format is not mentioned in the user guide). .svd seems to be the recommended format (.tcf format is not listed in the user guide).

____.png Reference information: Cortex Microcontroller Software Interface Standard (CMSIS)

On the other hand, the recommended format for Arm® DS / DS-5 seems to be .tcf.
The Arm® DS / DS-5 documentation also includes a description as Target Configuration File (TCF), which has the advantage of having a dedicated editor for editing.

____.png Reference information: Arm® Development Studio User Guide "Working with the Target Configuration Editor

____.png Reference information: Arm® DS-5 Debugger User Guide "Working with the Target Configuration Editor

Note that register definitions created in .svd format are automatically converted to .tcf format when Arm® DS/DS-5 reads the register definition file. In the end, the automatically converted .tcf will be used, so you can choose which format you prefer to use to create register definitions.

Personally, I recommend .tcf.
Not only is an editor available for editing, but I feel that .tcf XML has a tag structure that is easier to edit, even when editing XML directly with a text editor.

The details of the description method (XML tag structure) are beyond the scope of this article. Please refer to the existing definition files and documents for reference.

 

4. sample register definition file

For Arm® related peripherals that are not supported by the register view of Arm® DS / DS-5, a .tcf file that describes a register definition is shown below. Please use this file as a reference for register definition file descriptions.

The descriptions are intended to be used for debugging Cyclone® V SoC / Arria® V SoC without modification, but are not guaranteed to be correct (use at your own risk).

A version with modified base address definitions for the Arria® 10 SoC has also been created (again at user's risk).

Conclusion

In this issue, we described how to create your own register definitions for the Arm® DS / DS-5.
In the next (and final) article, we will describe how to display registers on the FPGA side.

 

Recommended Articles/Documents

Techniques for using Arm DS - Register View [1/3] Basic Settings
Techniques for using Arm DS - Register View [2/3] Register Definitions by Yourself
Techniques for using Arm DS - Register View [3/3] FPGA Side Register Display

 

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