Description.
In Altera® FPGAs, the required functions are realized in hardware by creating data to configure and connect the physical resources in the FPGA through the compilation (logic synthesis, placement, and routing) process on the design software (Quartus® Prime development software) and then downloading the compiled data into the FPGA. The compiled data is downloaded into the FPGA to realize the required functions as hardware.
In general, FPGAs are manufactured using SRAM-based technology, and internal data is not retained when the power is turned off. Therefore, it is necessary to store the compilation data in external nonvolatile memory and download the compilation data into the FPGA when the power is turned on. This mechanism is called "configuration," and Altera® FPGAs provide several configuration methods.
Despite the fact that the configuration circuit is relatively simple and is considered a "dead function," as described below, configuration support requests still account for about 20% of all support requests today, and a certain percentage of "configuration failures" and other problems still occur. This is due to the following factors. The following factors are considered to be responsible for this.
The circuit configuration and setting methods differ slightly from one FPGA generation to the next.
The volume of user manuals is increasing due to the addition of new configuration methods, encryption, remote updates, and other functions.
Increasing clock speeds to reduce configuration time due to increased FPGA capacity
Configuration is performed at the earliest stage, and if it fails, the FPGA will not function, so configuration troubles will have a significant impact on the customer's subsequent development process.
This document describes the simplest active serial configuration using Quad SPI (QSPI) Flash, including design considerations, common problems, and solutions.
Devices covered include Stratix® V, Arria® V, and Cyclone® V.
(There are some differences between the earlier families and Arria® 10 and Stratix® 10, so be sure to refer to the user manual for each device.)
<Contents
Introduction
What is Configuration
Design Guidelines
Debug Guidelines
Summary
Appendix
Documentation
Active Serial Configuration Design and Debug Guidelines (Rev. 4)
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