Introduction.
This article presents a sample design that accesses the three LPDDR4 lines in the Mpression Sulfur Type-A Development Kit (hereafter referred to as Sulfur ).
Overview of the Design
A block diagram is shown below.
The base design is the EMIF IP Example Design, which can be generated by Quartus and combines three LPDDR4 lines into one design (for more details on the Example Design, please refer to the user manual at the reference link ).
The JTAG to Avalon Master Bridge intel FPGA IP is connected to the mainband of the EMIF IP, and write/read to LPDDR4 can be performed from the System Console.
The AXILite_driver module implemented in the example design is connected to sideband, so that the calibration status can be checked via Signal Tap.
Figure 1] Block diagram of the design
Execution Results
The following figure shows the trace results of Signal Tap for each LPDDR4 interface. cal_done_rst_n port of AXILite_Driver shows the calibration status, and it can be confirmed that cal_done_rst_n=1 for each of them.
Figure 2 Signal Tap Result of 2B Bank
Figure 3 Signal Tap Result of 3A Bank
Figure 4] Signal Tap Result of 3B Bank
Equipment and Development Environment
Equipment
The following equipment is required to verify the operation of the sample design.
- Sulfur Type-A Development Kit "Sulfur Type-A Development Kit " x1
- FPGA download cable " Intel® FPGA Download Cable II " x1
Development environment
- FPGA development tools (Please select according to the file to be used.)
Point: FPGA development tools are available with a free license for the Agilex™ 5 E-Series.
How to obtain a Quartus® Prime Pro Edition free license file for Agilex™ 5 E development
Files Provided
| File No. | File Name / Download Link | Summary | Update Date |
| [1] | sulfur_emif_lpddr4x3_v2431.qar |
FPGA Design File (Quartus® Prime Pro Edition 24.3.1) |
2025.02.14 |
| [2] | sulfur_emif_lpddr4x3_v243.qar |
FPGA Design File (Quartus® Prime Pro Edition 24.3) |
2025.02.14 |
NOTES: OSC_CLK is set to 25 MHz in the above file.
Reference Links
- External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
- External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs
- Macnica Sulfur ~ Development Kit for Agilex™ 5 FPGA E-Series
- Using the System Console
- How to use Signal Tap