SoC Beginner's Guide - SoC Quick Tutorial (Atlas-SoC / DE10-Nano board version)

This "SoC Beginner's Guide" series is intended for novice users of Altera^® (Intel^®) SoC FPGAs.

Description

Altera^® (Intel^®) SoC FPGAs have a bus connection between the Arm^® core and the FPGA within the device. The intra-device connection is expected to solve the transfer rate shortage between the processor and FPGA and reduce the mounting area on the board.

This document allows users with the Cyclone^® V SoC FPGA Development Kit (DE0-Nano-SoC Kit / Atlas-SoC Kit or DE10-Nano Kit) to experience the respective development flow of SoC FPGA hardware and software.

Note:
The content for ver.20.1 and ver.18.1 is designed to be run on a computer with Windows 10.

Note:
The exercises for ver.20.1 use Arm^® Development Studio (Arm^® DS), and for ver.18.1 use Arm^® Development Studio 5 (DS-5™). Customers considering new development should use the version for ver.20.1.

Documentation

• Exercise Manual (ver. 20.1 / Rev. 4)
• Exercise Manual (ver. 18.1 / Rev. 2) (in Japanese)

Exercise Data

• Exercise data (ver. 20.1)
• Exercise data (ver. 18.1)