Introduction
Agilex™ 3 FPGAs can access PLL registers during operation to dynamically change output clock frequency and other settings. This feature is called dynamic reconfiguration. This article describes the procedure for changing the output clock frequency of the PLL using the development kit.
The environment checked this time is as follows.
Tool: Quartus® Prime Pro Edition v25.1.1
Development kit: Atum A3 Nano by Terasic
1. Dynamic Reconfiguration of I/O PLLs in Agilex™ 3
1-1 I/O PLL Types
Agilex™ 3 has the following two types of I/O PLLs that can be used in FPGA fabrics.
- Fabric-feeding I/O PLLs
- I/O bank I/O PLLs
For more information on each, please refer to the following links Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs - 1.2. PLLs Overview
These PLLs are located in the HSIO and HVIO banks as shown in Figure 1. The circuit configuration for dynamic reconfiguration depends on the bank in which they are located. As shown in Table 1, the I/O PLLs in the HSIO bank connect the EMIF Calibration IP. The I/O PLLs in the HVIO bank access the ports directly.
Figure 1. Agilex™ 3 I/O PLL Locations
(Source: Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs - 2.2.3. PLL Locations)
Table 1. Types of Dynamic Reconfiguration Circuits
| I/O Bank | I/O PLL | Dynamic Reconfiguration Circuit |
| HSIO Bank | I/O Bank I/O PLL | Configured on AXI4 Lite interface using EMIF calibration IP |
| Fabric-Feeding I/O PLL | ||
| HVIO Bank | Fabric-Feeding I/O PLL | Configured by accessing the reconfiguration port directly |
This article performs dynamic reconfiguration using the Fabric-feeding I/O PLLs in the HVIO bank. 1-2.
1-2. Preparing to Perform Dynamic Reconfiguration
To perform dynamic reconfiguration of I/O PLLs, it is necessary to set them in the GUI at the time of IP generation. For the HVIO bank, check "Enable dynamic reconfiguration of PLL" on the Dynamic Reconfiguration tab of the I/O PLL configuration screen. On the other hand, for I/O PLLs in the HSIO bank, check "Enable dynamic reconfiguration of PLL using Calibration IP" on the lower side.
Figure 2. Enable dynamic reconfiguration setting (I/O PLL of HVIO bank)
1-3. dynamic reconfiguration execution procedure
The dynamic reconfiguration is set in the I/O PLL register by the following procedure.
1. Enabling Reconfiguration (write address 0x10 bit[0]=1)
2. Set each register (multiple settings are possible)
3. Reset PLL (write address 0x80, bit[2]=1)
4. PLL Recalibration ( address 0x88, write bit[11] = 1)
The above procedure is based on the following link.
Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs - 6.4.3. Reconfiguring The I/O PLL
For details of each register, please refer to the following links.
Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs - 6.6.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration
The above procedure will change the I/O PLL settings. The register setting is Read-Modify-Write, and the bits other than the setting point are written without changing the read value. For other notes, please refer to the following links.
Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs - 6.3. Implementing HVIO I/O PLL Reconfiguration
2. checking actual device operation
2-1. creating a sample design
This time, we will use the System Console to set the I/O PLL registers and verify the dynamic reconfiguration operation. The block diagram of the design is shown in Figure 3. The output clock frequency of the PLL is set as C0: 10 MHz, C1: 20 MHz, and C2: 40 MHz. A counter operating at each clock frequency is implemented, and the upper bits of the counter are output to LEDs so that the LED blinking can be checked.
To access the system from the System Console, an IP called JTAG to Avalon-MM Master Bridge is used, but the interface is 32 bits. On the other hand, the interface for register access in the I/O PLL is 8 bits, so the data width is different. Therefore, a new module ("translator" in the figure) was created to convert between 32 bits and 8 bits x 4.
Figure 3. Block Diagram of the Created Design
2-2. Execution of System Console
First, compile the design and write the programming file (.sof) to the FPGA. For more information on programming, please refer to the following link.
Reference: Quartus® Getting Started Guide - How to Program a Device
Next, launch the System Console. To start, select Tools menu → System Debugging Tools → System Console in Quartus® Prime. For more information on the System Console, please refer to the following link
Reference: Using the FPGA System Debugging Tool "System Console
When launched, the screen shown in Figure 4 will appear. Double-click on the tabs to expand them.
Figure 4. System Console startup screen
Next, follow the steps described above. This time, we have created a simple Tcl (file name: reg_set.tcl) for accessing each register of the I/O PLL. This Tcl is located in the system_console folder. Type:
cd . /system_console
source reg_set.tcl
This will allow you to execute the procedures listed in reg_set.tcl and use them to change the output clock frequencies of C0, C1, and C2. This time, input the data as shown in Figure 5 so that C0, C1, and C2 have the same frequency.
Figure 5. System Console Input Contents
Now that the register values of C0, C1, and C2 are the same, the output clock frequency will also be the same.
In this design, the bit[23] of each counter is output to the LEDs, so matching the frequencies of C0, C1, and C2 will result in the same blinking cycle. Once the reset switch is pressed, each counter is reset and blinks at the same timing.
Figure 6. Reset switch and LEDs in the development kit
2-3 Checking with Signal Tap II
Changes in the PLL output clock frequency can be checked with the LEDs and also with Signal Tap II. The bit[2] of each counter is monitored. For details of Signal Tap II, please refer to the following link.
Reference material: Let's try FPGA on-chip debugging "Signal Tap
Figure 7 shows the results with the default settings and Figure 8 shows the results after dynamic reconfiguration. The sampling clock is asynchronous to each counter clock, so the waveform is distorted, but you can see that the counter period of C0, C1, and C2 are the same in Figure 8.
Figure 7. Counter Outputs in Initial Settings
Figure 8. Counter Output after Dynamic Reconfiguration
Access waveforms to each register of the I/O PLL are also attached for reference.
Figure 9 shows the waveform of writing 0x0F00081E to the C0 register (address 0x5c). The waveforms are written in 8-bit increments from the LSB side.
Figure 9. Waveform of writing 0x0F00081E to the C0 register (address 0x5c)
Figure 10 shows the read waveform of the C0 register (address 0x5c). The readdata is prefixed with 00h and then output in order from the LSB side.
Figure 10. Read waveform of C0 register (address 0x5c)
Figure 11 shows the waveform of writing 1 to bit[2] of the Reset PLL register (address 0x80).
Figure 11. Waveform of writing 1 to bit[2] of the Reset PLL register (address 0x80)
Figure 12 shows the overall waveform of Figure 11. Writing 1 to bit[2] of the Reset PLL register (address 0x80) causes the I/O PLL to enter a reset state, which stops the clock output and therefore also stops the counter. After that, writing 0 to bit[2] releases the reset.
Figure 12. Overall waveform when 1 is written to bit[2] of the Reset PLL register (address 0x80)
Conclusion
We have confirmed the dynamic reconfiguration behavior of the I/O PLL of Agilex™ 3. The design used is attached. We hope this article will be helpful.
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