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Is it possible to control GPIOs on the Hard Processor System (HPS) side of the Cyclone® V SoC / Arria V SoC from circuitry on the FPGA side?

Is it possible to control GPIOs on the Hard Processor System (HPS) side of the Cyclone® V SoC / Arria V SoC from circuitry on the FPGA side?

  • Updated

A mode called LOANIO is available as an interface to control HPS-specific I/O from the FPGA side (select LANIOxx in the Peripheral Pins tab of the Peripherals Mux Table in Platform Designer (formerly Qsys)).
(Select LANIOxx in the Peripherals Mux Table on the Peripheral Pins tab of the HPS configuration in Platform Designer (formerly Qsys))
When one or more ports of LoanIO are enabled, the following interfaces are added to the HPS so that these signals can be controlled.
　
　h2f_loan_in[66:0]
h2f_loan_out[66:0]
h2f_loan_oe[66:0]

H2FLoanIO.png

Notes
・The control can be done only after the boot loader (Preloader) is executed on the HPS side and the register setting of PinMux is done.
If the FPGA side has not been configured when the PinMux setting is completed, the output will be High until the
configuration is completed.

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Category: SoC
Tool: Quartus® Prime (Platform Designer)
Device: Cyclone® V

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