FAQ

• Are the dedicated analog input pins (ANAIN1/ ANAIN2) for the ADC in the MAX® 10 FPGA Hot-Socket compatible?
• Generating an IP with IP Catalog in Quartus® Prime Pro Edition ver. 21.1 causes an error.
• What are the register settings for automatic flow control of 16550 Compatible UART Core?
• When I set up the stack override command and build with reference to the document "Software Development with Nios II SBT, Section 2", I get the error nios2-elf-g++: error: =: No such file or directory.
• I posted a message in Japanese on the Community Forum, but it was not recognized correctly. What should I pay attention to?
• Can I use Cyclone® V with the Altera® HLS (High Level Synthesis) compiler?
• I ran DSE II (Design Space Exproler II) on Quartus® Prime Pro Edition and Progress is still at 0%. No errors are occurring.
• How can I make the signal names displayed in the Wave window of ModelSim* - Altera® FPGA Edition to be only short signal names instead of full paths?
• Why do I see duplicate channels when using TTK (Transceiver Toolkit) in a Transceiver Duplex configuration?
• When I run "Run As ModelSim" from Nios® II SBT (Software Build Tools for Eclipse), the simulation does not proceed and stops.
• Nios® II SBT (Software Build Tools) for Eclipse cannot execute Build.
• In Nios® II SBT (Software Build Tools) for Eclipse, the enale_small_driver setting is not reflected and the grayed-out conditional branch in the source code does not switch.
• When compiling (Fitter) with Quartus® Prime, a pin named "termination_blk0~_rzq_pad" is generated, which cannot be assigned to a pin and causes an error. Please let me know how to solve this problem.
• I cannot find the PDN Tool for Cyclone® 10 LP. How do I do a decoupling capacitor estimation?
• Is there any documentation that shows which BANK the Hard Memory Controller can be placed in?
• When I tried to simulate a PLL, there was a slight difference in the output clock frequency between the RTL simulation file *.v and the gate-level simulation file *.vo. Why is this?
• If the Modular ADC Core IP is used alone and not within Platform Designer, is the reset input signal an asynchronous reset? How long is the reset period?
• I created a 5Gbps design with Cyclone® V Native PHY, but a Fitter Error occurs. Please let me know the cause.
• Is the maximum output frequency of Cyclone® V I/O defined as a specification?
• I want to write configuration data from the CPU outside the FPGA to the configuration ROM (MT25Q) using the Generic Serial Flash Interface IP inside the FPGA. What format should I use for the data file to be written?
• Does Quartus® Prime Programmer have a factory default PFL image for MAX® 10?
• An error occurs when Generate HDL is run on a Platform Designer system for a design containing Nios® II.
• I want to use Quartus® Prime with the Tcl command.
• JTAG is not recognized by MAX® 10. Is it related to the fact that the Exposed Pad on the back side of the EQFP package is not connected to GND?
• I tried to run the Board Test System with the Cyclone® 10 GX Development Kit, but it failed. I use J9 connector (Embedded Intel FPGA Download Cable II) to connect to the board.
• Does the Application Image require a Remote Update IP when using the Remote System Upgrade feature?
• Quartus® Prime Pro Edition and Standard Edition have a software license agreement (EULA), but is there an EULA for the Lite Edition?
• Can I change the delay value from the clock input pin with MAX® 10?
• The Board Test System (BTS) does not recognize the device in the Cyclone® 10 GX Development Kit. What can I do about it?
• Is it safe to use a single regulator for a MAX® 10 single power supply device with all I/O banks at 3.3V and no ADC?