When I tried to simulate a PLL, there was a slight difference in the output clock frequency between the RTL simulation file *.v and the gate-level simulation file *.vo. Why is this?

The actual frequency value set in the PLL is the Actual Settings displayed in the PLL Setting Wizard, such as [Output Clocks]→[clk c0].
If there is a difference in the actual frequency setting (Actual Setting) compared to the set frequency, the output clock frequency will differ between *.v and *.vo as shown here.

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Category: Simulation
Tool: ModelSim®
Device: All