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An error occurs when Generate HDL is run on a Platform Designer system for a design containing Nios® II.

An error occurs when Generate HDL is run on a Platform Designer system for a design containing Nios® II.

  • Updated

＜Error message

 Error: add_fileset_file: No such file <quartus_prime_install_dir>/ip/altera/altera_nios2_gen2_rtl/cadence/altera_nios2_gen2_rtl_ module.sv

In Intel® Quartus® Prime Standard Edition 19.1, 20.1, and 20.1.1 (for Windows OS), when generating RTL for a Platform Designer system that includes Nios® II, if you specify a simulation model The above error message may appear.
A patch has been released for Quartus® Prime Standard Edition 20.1.1.
If you are using Quartus® Prime Standard Edition 19.1 and 20.1, please upgrade to ver. 20.1.1, then install
Quartus® Prime Standard Edition 20.1.1, and then install the patch additionally.

Patch files can be obtained from the following page
<KDB> Error: add_fileset_file: No such file C:/intelFPGA/20.1std/ip/altera/altera_nios2_gen2_rtl/cadence/altera_nios2_gen2_rtl_ module.sv

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Category:Quartus® Prime
Tools:Quartus® Prime
Devices:-

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