FAQ

• In a design using the MAX® 10 PLL, a non-clock signal pll_lock_sync was reported in the Unconstrained Paths => Clock Status Summary of the timing analysis. Why was this signal recognized as a clock when it is a Locked signal of the PLL?
• If I program a .pof / .jic file generated by an older version of Quartus® Prime/II, do I need to use the same version of Programmer?
• When installing the USB-Blaster II (or USB-Blaster) driver on Windows® 10, I got an error log stating "A problem occurred while installing the device driver.
• Why are the PLLs for ALTLVDS_RX and ALTLVDS_TX not shared even if the Use shared PLL for receivers and transmitters option is enabled?
• I get a FLEXlm software error when compiling with Quartus® Prime Standard Edition. How can I solve this problem?
• When simulating ALTLVDS_RX IP at the RTL level, an error occurs in the "lvds_rx_reg_setting" parameter. (Both VHDL/Verilog).
• In Quartus® Prime 17.0, the MAX® 10 single power supply U324 package is not available.
• When performing an Arria® 10 I/O PLL Reconfiguration, a register is set for the PLL Reconfig Intel FPGA IP, but the value written to the register is not written correctly. Why is this?
• Is it possible to process FPGA internal pull-ups on the LVDS pins of the Cyclone® V?
• Nativelink simulation of a circuit using On-Chip Flash IP in MAX® 10 with ModelSim*-Altera® FPGA Edition fails with Load.
• A proven design with an RTL simulation of an ADC in a MAX® 10 FPGA in ModelSim* , ported to another directory and performing the same task, results in an error message.
• What is the burst operation of HBM2 (High Bandwidth Memory) IP cores?
• How can I perform file transfer and write to the Flash memory (QSPI, NAND) of the HPS (Hard Processor System) via JTAG?
• I am configuring a PCI-Express (PCIe) IP with CvP on an Arria® 10 device, at what point in the configuration should the PCIe Refclk be stable?
• When using LVDS_Rx IP in DPA mode with Arria® 10, is it necessary to calculate RSKM etc. and add SDC constraints?
• It is recommended to pull up TDI/TMS of JTAG of Cyclone® 10 LP with VCCA (+2.5V), but even if 3.3V is connected to VCCIO1, is it OK to pull up with 2.5V?
• I want to default ModelSim® compilation to System Verilog.
• Can I customize the window layout and size when ModelSim® starts up?
• How do I access the Slave inside Platform Designer from an external CPU using the SPI Slave to Avalon Master Bridge Core?
• Is there a rule for the order in which addresses are set when issuing the RSU_IMAGE_UDATE command in RSU (Remote System Update) on Stratix® 10?
• When I use $fopen to output a file in a simulation in ModelSim®, the number of files is limited to 30. What is the workaround?
• I am trying to generate an MSI interrupt on a PCIe (PCI-Express) IP (Avalon-ST Interface) by asserting "app_msi_req", but "app_msi_ack" is not asserted.
• CTLE has two settings, HG (High Gain) mode and HDR (High Data Rate) mode. Which setting should I use when using PCIe (PCI-Express) IP with Arria® 10?
• Placing two EMIF (External Memory Interface) IP cores on the same column in Arria® 10 results in a Fitter Error.
• Is it possible to generate Message TLPs such as Correctable / Fatal / Non-Fatal Error on PCI Express (PCIe) at arbitrary timing from the user circuit side?
• Example Design generation fails when using the JESD204B IP with Wrapper Options = PHY Only setting on Stratix® 10 devices.
• Can I use the readwaittime parameter of the Avalon® Interface together with the waitrequest signal?
• My Nios® II simulation stops halfway through.
• Null Pointer error in the BSP Editor of Nios® II SBT (Software Build Tools for Eclipse).
• In the Current Drawn from Voltage Supplies Summary of the Power Analyzer Tool, VCCIO_HPS and VCCPD_HPS are 0.00mA, but is there any current consumption?